HCS08 datasheet(158/290 Pages) MOTOROLA

158 / 290 page

Timer/PWM (TPM) Module

MC9S08GB/GT

158

MOTOROLA

The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a

modulo counter, or an up/down counter when the TPM is configured for center-aligned PWM. The TPM

counter (when operating in normal up-counting mode) provides the timing reference for the input capture,

output compare, and edge-aligned PWM functions. The timer counter modulo registers,

TPMxMODH:TPMxMODL, control the modulo value of the counter. (The values $0000 or $FFFF

effectively make the counter free running.) Software can read the counter value at any time without

affecting the counting sequence. Any write to either byte of the TPMxCNT counter resets the counter

regardless of the data value written.

All TPM channels are programmable independently as input capture, output compare, or buffered

edge-aligned PWM channels.

10.4 Pin Descriptions

Table 10-1 shows the MCU pins related to the TPM modules. When TPMxCH0 is used as an external

clock input, the associated TPM channel 0 may not use the pin. (Channel 0 could still be used in output

compare mode as a software timer.) When any of the pins associated with the timer is acting as a

general-purpose input or as a timer input, a passive pullup can be enabled. After reset, the TPM modules

are disabled and all pins default to general-purpose inputs with the passive pullups disabled.

10.4.1 External TPM Clock Sources

When control bits CLKSB:CLKSA in the timer status and control register are set to 1:1, the prescaler and

subsequently the 16-bit counter for TPMx are driven by an external clock source connected to the

TPMxCH0 pin. A synchronizer is needed between the external clock and the rest of the TPM. This

synchronizer is clocked by the bus clock so the frequency of the external source must be less than one-half

the frequency of the bus rate clock. The upper frequency limit for this external clock source is specified to

be one-fourth the bus frequency to conservatively accommodate duty cycle and phase-locked loop (PLL)

or frequency-locked loop (FLL) frequency jitter effects.

When the TPM is using the channel 0 pin for an external clock, the corresponding ELS0B:ELS0A control

bits should be set to 0:0 so channel 0 is not trying to use the same pin.

10.4.2 TPMxCHn — TPMx Channel n I/O Pins

Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the

configuration of the channel. In some cases no pin function is needed so the pin reverts to being controlled

by general-purpose I/O controls. When a timer has control of a port pin, the port data and data direction

registers do not affect the related pin(s). See the Pins and Connections section for additional information

about shared pin functions.

HCS08 bảng dữ liệu(PDF) 158 Page - Motorola, Inc