HCS08 datasheet(155/290 Pages) MOTOROLA

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Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

155

MC9S08GB/GT

Section 10 Timer/PWM (TPM) Module

10.1 Introduction

The MC9S08GB/GT includes two independent timer/PWM (TPM) modules which support traditional

input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on each channel.

A control bit in each TPM configures all channels in that timer to operate as center-aligned PWM

functions. In each of these two TPMs, timing functions are based on a separate 16-bit counter with

prescaler and modulo features to control frequency and range (period between overflows) of the time

reference. This timing system is ideally suited for a wide range of control applications, and the

center-aligned PWM capability on the 3-channel TPM extends the field of applications to motor control

in small appliances.

The fixed system clock XCLK is normally the oscillator rate divided by two (ICGERCLK/2). If the PLL

or FLL is engaged and locked, and the bus rate (BUSCLK) is not at least two times the ICGERCLK

frequency, XCLK equals BUSCLK instead of ICGERCLK/2.

10.2 Features

The timer system in the MC9S08GBxx includes a 3-channel TPM1 and a separate 5-channel TPM2; the

timer system in the MC9S08GTxx includes two 2-channel modules, TPM1 and TPM2. Timer system

features include:

•

A total of eight channels:

–

Each channel may be input capture, output compare, or buffered edge-aligned PWM

–

Rising-edge, falling-edge, or any-edge input capture trigger

–

Set, clear, or toggle output compare action

–

Selectable polarity on PWM outputs

•

Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all

channels

•

Clock source to prescaler for each TPM is independently selectable as bus clock, fixed system

clock, or an external pin:

–

Prescale taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128

–

Fixed system clock (XCLK) and pin paths are synchronized

–

External clocks shared with TPMxCH0 timer channel pins

•

16-bit free-running or up/down (CPWM) count operation

•

16-bit modulus register to control counter range

•

Timer system enable

•

One interrupt per channel plus terminal count interrupt

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