HCS08 datasheet(142/290 Pages) MOTOROLA

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Parallel Input/Output

MC9S08GB/GT

142

MOTOROLA

PTDDn — Port D Data Register Bit n (n = 0–7)

For port D pins that are inputs, reads return the logic level on the pin. For port D pins that are

configured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic

level is driven out the corresponding MCU pin.

Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also

configures all port pins as high-impedance inputs with pullups disabled.

PTDPEn — Pullup Enable for Port D Bit n (n = 0–7)

For port D pins that are inputs, these read/write control bits determine whether internal pullup devices

are enabled. For port D pins that are configured as outputs, these bits are ignored and the internal pullup

devices are disabled.

1 = Internal pullup device enabled.

0 = Internal pullup device disabled.

PTDSEn — Slew Rate Control Enable for Port D Bit n (n = 0–7)

For port D pins that are outputs, these read/write control bits determine whether the slew rate

controlled outputs are enabled. For port D pins that are configured as inputs, these bits are ignored.

1 = Slew rate control enabled.

0 = Slew rate control disabled.

PTDDDn — Data Direction for Port D Bit n (n = 0–7)

These read/write bits control the direction of port D pins and what is read for PTDD reads.

1 = Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.

0 = Input (output driver disabled) and reads return the pin value.

8.6.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD)

Port E includes eight general-purpose I/O pins that share with the SCI1 and SPI modules. Port E pins used

as general-purpose I/O pins are controlled by the port E data (PTED), data direction (PTEDD), pullup

enable (PTEPE) and slew rate control (PTESE) registers.

If the SCI1 takes control of a port E pin, the corresponding PTEDD bit are ignored. PTESE can be used to

provide slew rate on the SCI1 transmit pin, TxD1. PTEPE can be used, provided the corresponding

PTEDD bit is a logic 0, to provide a pullup device on the SCI1 receive pin, RxD1.

If the SPI takes control of a port E pin, the corresponding PTEDD bit are ignored. PTESE can be used to

provide slew rate on the SPI serial output pin (MOSI or MISO) and serial clock pin (SPCLK) depending

on the SPI operational mode. PTEPE can be used, provided the corresponding PTEDD bit is a logic 0, to

provide a pullup device on the SPI serial input pins (MOSI or MISO) and slave select pin (SS) depending

on the SPI operational mode.

Reads of PTED will return the logic value of the corresponding pin, provided PTEDD is a logic 0.

HCS08 bảng dữ liệu(PDF) 142 Page - Motorola, Inc