HCS08 datasheet(138/290 Pages) MOTOROLA

138 / 290 page

Parallel Input/Output

MC9S08GB/GT

138

MOTOROLA

PTASEn — Slew Rate Control Enable for Port A Bit n (n = 0–7)

For port A pins that are outputs, these read/write control bits determine whether the slew rate

controlled outputs are enabled. For port A pins that are configured as inputs, these bits are ignored.

1 = Slew rate control enabled.

0 = Slew rate control disabled.

PTADDn — Data Direction for Port A Bit n (n = 0–7)

These read/write bits control the direction of port A pins and what is read for PTAD reads.

1 = Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.

0 = Input (output driver disabled) and reads return the pin value.

8.6.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD)

Port B includes eight general-purpose I/O pins that share with the ATD function. Port B pins used as

general-purpose I/O pins are controlled by the port B data (PTBD), data direction (PTBDD), pullup enable

(PTBPE) and slew rate control (PTBSE) registers.

If the ATD takes control of a port B pin, the corresponding PTBDD, PTBSE, PTBPE bits are ignored.

When a port B pin is being used as an ATD pin, reads of PTBD will return a logic 0 of the corresponding

pin, provided PTBDD is a logic 0.

Figure 8-10 Port B Registers

PTBD

Bit 7

654321

Bit 0

Read:

PTBD7

PTBD6

PTBD5

PTBD4

PTBD3

PTBD2

PTBD1

PTBD0

Write:

Reset:

00000000

PTBPE

Read:

PTBPE7

PTBPE6

PTBPE5

PTBPE4

PTBPE3

PTBPE2

PTBPE1

PTBPE0

Write:

Reset:

00000000

PTBSE

Read:

PTBSE7

PTBSE6

PTBSE5

PTBSE4

PTBSE3

PTBSE2

PTBSE1

PTBSE0

Write:

Reset:

00000000

PTBDD

Read:

PTBDD7

PTBDD6

PTBDD5

PTBDD4

PTBDD3

PTBDD2

PTBDD1

PTBDD0

Write:

Reset:

00000000

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