HCS08 datasheet(140/290 Pages) MOTOROLA

140 / 290 page

Parallel Input/Output

MC9S08GB/GT

140

MOTOROLA

Figure 8-11 Port C Registers

PTCDn — Port C Data Register Bit n (n = 0–7)

For port C pins that are inputs, reads return the logic level on the pin. For port C pins that are configured

as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic

level is driven out the corresponding MCU pin.

Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also

configures all port pins as high-impedance inputs with pullups disabled.

PTCPEn — Pullup Enable for Port C Bit n (n = 0–7)

For port C pins that are inputs, these read/write control bits determine whether internal pullup devices

are enabled. For port C pins that are configured as outputs, these bits are ignored and the internal pullup

devices are disabled.

1 = Internal pullup device enabled.

0 = Internal pullup device disabled.

PTCSEn — Slew Rate Control Enable for Port C Bit n (n = 0–7)

For port C pins that are outputs, these read/write control bits determine whether the slew rate controlled

outputs are enabled. For port B pins that are configured as inputs, these bits are ignored.

1 = Slew rate control enabled.

0 = Slew rate control disabled.

PTCD

Bit 7

654321

Bit 0

Read:

PTCD7

PTCD6

PTCD5

PTCD4

PTCD3

PTCD2

PTCD1

PTCD0

Write:

Reset:

00000000

PTCPE

Read:

PTCPE7

PTCPE6

PTCPE5

PTCPE4

PTCPE3

PTCPE2

PTCPE1

PTCPE0

Write:

Reset:

00000000

PTCSE

Read:

PTCSE7

PTCSE6

PTCSE5

PTCSE4

PTCSE3

PTCSE2

PTCSE1

PTCSE0

Write:

Reset:

00000000

PTCDD

Read:

PTCDD7

PTCDD6

PTCDD5

PTCDD4

PTCDD3

PTCDD2

PTCDD1

PTCDD0

Write:

Reset:

00000000

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