HCS08 datasheet(144/290 Pages) MOTOROLA

144 / 290 page

Parallel Input/Output

MC9S08GB/GT

144

MOTOROLA

PTEDDn — Data Direction for Port E Bit n (n = 0–7)

These read/write bits control the direction of port E pins and what is read for PTED reads.

1 = Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.

0 = Input (output driver disabled) and reads return the pin value.

8.6.6 Port F Registers (PTFD, PTFPE, PTFSE, and PTFDD)

Port F includes eight general-purpose I/O pins that are not shared with any peripheral module. Port F pins

used as general-purpose I/O pins are controlled by the port F data (PTFD), data direction (PTFDD), pullup

enable (PTFPE), and slew rate control (PTFSE) registers.

Figure 8-14 Port F Registers

PTFDn — Port PTF Data Register Bit n (n = 0–7)

For port F pins that are inputs, reads return the logic level on the pin. For port F pins that are configured

as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic

level is driven out the corresponding MCU pin.

Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also

configures all port pins as high-impedance inputs with pullups disabled.

PTFD

Bit 7

654321

Bit 0

Read:

PTFD7

PTFD6

PTFD5

PTFD4

PTFD3

PTFD2

PTFD1

PTFD0

Write:

Reset:

00000000

PTFPE

Read:

PTFPE7

PTFPE6

PTFPE5

PTFPE4

PTFPE3

PTFPE2

PTFPE1

PTFPE0

Write:

Reset:

00000000

PTFSE

Read:

PTFSE7

PTFSE6

PTFSE5

PTFSE4

PTFSE3

PTFSE2

PTFSE1

PTFSE0

Write:

Reset:

00000000

PTFDD

Read:

PTFDD7

PTFDD6

PTFDD5

PTFDD4

PTFDD3

PTFDD2

PTFDD1

PTFDD0

Write:

Reset:

00000000

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