HCS08 datasheet(136/290 Pages) MOTOROLA

136 / 290 page

Parallel Input/Output

MC9S08GB/GT

136

MOTOROLA

8.5 Stop Modes

Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An

explanation of I/O behavior for the various stop modes follows:

•

Stop1 mode is the lowest current stop mode. All I/O states are lost in this mode. Upon recovery from

stop1, all I/O must be initialized as if the MCU were undergoing an initial power-up.

•

Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as

before the STOP instruction was executed. CPU register status and the state of I/O registers should

be saved in RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon

recovery from stop2 mode, before accessing any I/O, the user should examine the state of the PPDF

bit in the SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had

occurred. If the PPDF bit is 1, I/O data previously stored in RAM, before the STOP instruction was

executed, peripherals may require being initialized and restored to their pre-stop condition. The user

must then write a 1 to the PPDACK bit in the SPMSC2 register. Access to I/O is now permitted

again in the user’s application program.

•

In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon

recovery, normal I/O function is available to the user.

8.6 Parallel I/O Registers and Control Bits

This section provides information about all registers and control bits associated with the parallel I/O ports.

Refer to tables in the Memory section for the absolute address assignments for all parallel I/O registers.

This section refers to registers and control bits only by their names. A Motorola-provided equate or header

file normally is used to translate these names into the appropriate absolute addresses.

8.6.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD)

Port A includes eight pins shared between general-purpose I/O and the KBI module. Port A pins used as

general-purpose I/O pins are controlled by the port A data (PTAD), data direction (PTADD), pullup enable

(PTAPE) and slew rate control (PTASE) registers.

If the KBI takes control of a port A pin, the corresponding PTASE bit is ignored since the pin functions as

an input. As long as PTADD is a logic 0, the PTAPE controls the pullup enable for the KBI function. Reads

of PTAD will return the logic value of the corresponding pin, provided PTADD is a logic 0.

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