HCS08 datasheet(174/316 Pages) NXP

174 / 316 page

Inter-Integrated Circuit (S08IICV2)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

174

Freescale Semiconductor

11.4.1.8

Handshaking

The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold

the SCL low after completion of one byte transfer (9 bits). In such a case, it halts the bus clock and forces

the master clock into wait states until the slave releases the SCL line.

11.4.1.9

Clock Stretching

The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After

the master has driven SCL low the slave can drive SCL low for the required period and then release it. If

the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low

period is stretched.

11.4.2

10-bit Address

For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of

read/write formats are possible within a transfer that includes 10-bit addressing.

11.4.2.1

Master-Transmitter Addresses a Slave-Receiver

The transfer direction is not changed (see Table 11-10). When a 10-bit address follows a start condition,

each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own

address and tests whether the eighth bit (R/W direction bit) is 0. More than one device can find a match

and generate an acknowledge (A1). Then, each slave that finds a match compares the eight bits of the

second byte of the slave address with its own address. Only one slave finds a match and generates an

acknowledge (A2). The matching slave remains addressed by the master until it receives a stop condition

(P) or a repeated start condition (Sr) followed by a different slave address.

After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an IIC

interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this

interrupt.

11.4.2.2

Master-Receiver Addresses a Slave-Transmitter

The transfer direction is changed after the second R/W bit (see Table 11-11). Up to and including

acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a

slave-receiver. After the repeated start condition (Sr), a matching slave remembers that it was addressed

before. This slave then checks whether the first seven bits of the first byte of the slave address following

Sr are the same as they were after the start condition (S) and tests whether the eighth (R/W) bit is 1. If there

is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge A3.

The slave-transmitter remains addressed until it receives a stop condition (P) or a repeated start condition

(Sr) followed by a different slave address.

Slave Address 1st 7 bits

R/W

Slave Address 2nd byte

Data

...

Data

A/A

11110 + AD10 + AD9

AD[8:1]

Table 11-10. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address

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