HCS08 datasheet(63/316 Pages) NXP

63 / 316 page

Chapter 5 Resets, Interrupts, and General System Control

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

The COP counter is initialized by the first writes to the SOPT1 and SOPT2 registers after any system reset.

Subsequent writes to SOPT1 and SOPT2 have no effect on COP operation. Even if the application will use

the reset default settings of COPT, COPCLKS, and COPW bits, the user should write to the write-once

SOPT1 and SOPT2 registers during reset initialization to lock in the settings. This will prevent accidental

changes if the application program gets lost.

The write to SRS that services (clears) the COP counter should not be placed in an interrupt service routine

(ISR) because the ISR could continue to be executed periodically even if the main application program

fails.

If the bus clock source is selected, the COP counter does not increment while the MCU is in background

debug mode or while the system is in stop mode. The COP counter resumes when the MCU exits

background debug mode or stop mode.

If the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either

background debug mode or stop mode and begins from zero upon exit from background debug mode or

stop mode.

5.5

Interrupts

Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine

(ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other

than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events

such as an edge on a pin interrupt or a timer-overflow event. The debug module can also generate an SWI

under certain circumstances.

If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The

CPU will not respond unless the local interrupt enable is a 1 to enable the interrupt and the I bit in the CCR

is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which

prevents all maskable interrupt sources. The user program initializes the stack pointer and performs other

system setup before clearing the I bit to allow the CPU to respond to interrupts.

When the CPU receives a qualified interrupt request, it completes the current instruction before responding

to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction

and consists of:

•

Saving the CPU registers on the stack

•

Setting the I bit in the CCR to mask further interrupts

•

Fetching the interrupt vector for the highest-priority interrupt that is currently pending

•

Filling the instruction queue with the first three bytes of program information starting from the

address fetched from the interrupt vector locations

While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of

another interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is

restored to 0 when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit

can be cleared inside an ISR (after clearing the status flag that generated the interrupt) so that other

interrupts can be serviced without waiting for the first service routine to finish. This practice is not

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