HCS08 datasheet(88/316 Pages) NXP

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Chapter 6 Parallel Input/Output Control

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

6.6.3

Port C Registers

Port C is controlled by the registers listed below.

6.6.3.1

Port C Data Register (PTCD)

6.6.3.2

Port C Data Direction Register (PTCDD)

321

000

PTCD3

PTCD2

PTCD1

PTCD0

Reset:

000

Figure 6-19. Port C Data Register (PTCD)

Table 6-18. PTCD Register Field Descriptions

Field

Description

3:0

PTCD[3:0]

Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin. For port C

pins that are configured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures

all port pins as high-impedance inputs with pull-ups disabled.

321

000

PTCDD3

PTCDD2

PTCDD1

PTCDD0

Reset:

000

Figure 6-20. Port C Data Direction Register (PTCDD)

Table 6-19. PTCDD Register Field Descriptions

Field

Description

3:0

PTCDD[3:0]

Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for

PTCD reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.

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