HCS08 datasheet(36/316 Pages) NXP

36 / 316 page

Chapter 3 Modes of Operation

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

Most background commands are not available in stop mode. The memory-access-with-status commands

do not allow memory access, but they report an error indicating that the MCU is in either stop or wait

mode. The BACKGROUND command can be used to wake the MCU from stop and enter active

background mode if the ENBDM bit is set. After entering background debug mode, all background

commands are available.

3.6.2

Stop2 Mode

Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most

of the internal circuitry of the MCU is powered off in stop2 with the exception of the RAM. Upon entering

stop2, all I/O pin control signals are latched so that the pins retain their states during stop2.

Exit from stop2 is performed by asserting the wake-up pin (RESET) on the MCU.

In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled.

Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR):

•

All module control and status registers are reset

•

The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVD

trip point (low trip point selected due to POR)

•

The CPU takes the reset vector

In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This flag is used to

direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched

until a 1 is written to PPDACK in SPMSC2.

To maintain I/O states for pins that were configured as general-purpose I/O before entering stop2, the user

must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers

before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to

PPDACK, then the pins will switch to their reset states when PPDACK is written.

For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that

interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before

writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O

latches are opened.

3.6.3

On-Chip Peripheral Modules in Stop Modes

When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even

in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,

clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.2, “Stop2

Mode,” and Section 3.6.1, “Stop3 Mode,” for specific information on system behavior in stop modes.

HCS08 bảng dữ liệu(PDF) 36 Page - NXP Semiconductors