HCS08 datasheet(29/316 Pages) NXP

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Chapter 2 Pins and Connections

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

The voltage measured on the internally pulled up RESET pin will not be

pulled to VDD. The internal gates connected to this pin are pulled to VDD. If

the RESET pin is required to drive to a VDD level an external pullup should

be used.

NOTE

In EMC-sensitive applications, an external RC filter is recommended on the

RESET. See Figure 2-4 for an example.

2.2.4

Background / Mode Select (BKGD/MS)

During a power-on-reset (POR) or background debug force reset (see Section 5.7.2, “System Background

Debug Force Reset Register (SBDFR),” for more information), the BKGD/MS pin functions as a mode

select pin. Immediately after any reset, the pin functions as the background pin and can be used for

background debug communication. The BKGD/MS pin contains an internal pullup device.

If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of the

internal reset after a POR or force BDC reset. If a debug system is connected to the 6-pin standard

background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a

background debug force reset, which will force the MCU to active background mode.

The BKGD pin is used primarily for background debug controller (BDC) communications using a custom

protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC

clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance

connected to the BKGD/MS pin that could interfere with background serial communications.

Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol

provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from

cables and the absolute value of the internal pullup device play almost no role in determining rise and fall

times on the BKGD pin.

2.2.5

General-Purpose I/O and Peripheral Ports

The MC9S08SG8 series of MCUs support up to 16 general-purpose I/O pins which are shared with

on-chip peripheral functions (timers, serial I/O, ADC, etc.).

When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,

software can select one of two drive strengths and enable or disable slew rate control. When a port pin is

configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a

pull-up device. Immediately after reset, all of these pins are configured as high-impedance

general-purpose inputs with internal pull-up devices disabled.

When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is

read from port data registers even though the peripheral module controls the pin direction by controlling

the enable for the pin’s output buffer. For information about controlling these pins as general-purpose I/O

pins, see Chapter 6, “Parallel Input/Output Control.”

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