HCS08 datasheet(35/316 Pages) NXP

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Chapter 3 Modes of Operation

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various

conditions. The selected mode is entered following the execution of a STOP instruction.

3.6.1

Stop3 Mode

Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The

states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.

Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time

counter (RTC), LVD system, ACMP, ADC, SCI, or any pin interrupts.

If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking

the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the

appropriate interrupt vector.

3.6.1.1

LVD Enabled in Stop Mode

The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below

the LVD voltage. For configuring the LVD system for interrupt or reset, refer to 5.6, “Low-Voltage Detect

(LVD) System”. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time

the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.

For the ADC to operate in stop mode, the LVD must be enabled when entering stop3.

For the ACMP to operate in stop mode with compare to internal bandgap option, the LVD must be enabled

when entering stop3.

3.6.1.2

Active BDM Enabled in Stop Mode

Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This

STOP instruction, the system clocks to the background debug logic remain active when the MCU enters

stop mode. Because of this, background debug communication remains possible. In addition, the voltage

regulator does not enter its low-power standby state but maintains full internal regulation.

Table 3-1. Stop Mode Selection

STOPE

ENBDM 1

1 ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see Section 17.4.1.1, “BDC Status and

Control Register (BDCSCR)”.

LVDE

LVDSE

PPDC

Stop Mode

Stop modes disabled; illegal opcode reset if STOP instruction executed

Stop3 with BDM enabled 2

2 When in Stop3 mode with BDM enabled, The S

IDD will be near RIDD levels because internal clocks are enabled.

Both bits must be 1

Stop3 with voltage regulator active

Either bit a 0

Stop3

Either bit a 0

Stop2

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