HCS08 datasheet(67/316 Pages) NXP

67 / 316 page

Chapter 5 Resets, Interrupts, and General System Control

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

5.6

Low-Voltage Detect (LVD) System

The MC9S08SG8 includes a system to protect against low voltage conditions in order to protect memory

contents and control MCU system states during supply voltage variations. The system is comprised of a

power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and detection. The LVD

circuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon entering any of the stop

modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then the MCU cannot enter

stop2, and the current consumption in stop3 with the LVD enabled will be higher.

5.6.1

Power-On Reset Operation

When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset

rearm voltage level, VPOR, the POR circuit will cause a reset condition. As the supply voltage rises, the

LVD circuit will hold the MCU in reset until the supply has risen above the low voltage detection low

threshold, VLVDL. Both the POR bit and the LVD bit in SRS are set following a POR.

5.6.2

Low-Voltage Detection (LVD) Reset Operation

The LVD can be configured to generate a reset upon detection of a low voltage condition by setting

LVDRE to 1. The low voltage detection threshold is determined by the LVDV bit. After an LVD reset has

occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the low

voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or POR.

5.6.3

Low-Voltage Warning (LVW) Interrupt Operation

The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is

approaching the low voltage condition. When a low voltage warning condition is detected and is

configured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt

request will occur.

5.7

Reset, Interrupt, and System Control Registers and Control Bits

One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space

are related to reset and interrupt systems.

Refer to Table 4-2 and Table 4-3 in Chapter 4, “Memory,” of this data sheet for the absolute address

assignments for all registers. This section refers to registers and control bits only by their names. A

Freescale-provided equate or header file is used to translate these names into the appropriate absolute

addresses.

Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief

descriptions of these bits are provided here, the related functions are discussed in greater detail in

Chapter 3, “Modes of Operation.”

HCS08 bảng dữ liệu(PDF) 67 Page - NXP Semiconductors