HCS08 datasheet(78/316 Pages) NXP

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Chapter 6 Parallel Input/Output Control

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

6.4

Pin Interrupts

Port A[3:0] and port B[3:0] pins can be configured as external interrupt inputs and as an external means

of waking the MCU from stop3 or wait low-power modes.

The block diagram for the pin interrupts is shown Figure 6-2.

Figure 6-2. Pin Interrupt Block Diagram

Writing to the PTxPSn bits in the port interrupt pin enable register (PTxPS) independently enables or

disables each port pin interrupt. Each port can be configured as edge sensitive or edge and level sensitive

based on the PTxMOD bit in the port interrupt status and control register (PTxSC). Edge sensitivity can be

software programmed to be either falling or rising; the level can be either low or high. The polarity of the

edge or edge and level sensitivity is selected using the PTxESn bits in the port interrupt edge select register

(PTxES).

Synchronous logic is used to detect edges. Prior to detecting an edge, enabled pin interrupt inputs must be

at the deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic

1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle.

A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1

during the next cycle.

6.4.1

Edge Only Sensitivity

A valid edge on an enabled pin interrupt will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt

request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in

PTxSC.

6.4.2

Edge and Level Sensitivity

A valid edge or level on an enabled pin interrupt will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an

interrupt request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to

PTxACK in PTxSC provided all enabled pin interrupt inputs are at their deasserted levels. PTxIF will

remain set if any enabled pin interrupt is asserted while attempting to clear by writing a 1 to PTxACK.

PTxESn

CLR

VDD

PTxMOD

PTxIE

PORT

INTERRUPT FF

PTxACK

RESET

SYNCHRONIZER

PTxIF

STOP BYPASS

STOP

BUSCLK

PTxPSn

PTxPS0

PTxES0

PIxn

PIx

PTx

INTERRUPT

REQUEST

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