HCS08 datasheet(79/316 Pages) NXP

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Chapter 6 Parallel Input/Output Control

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

6.4.3

Pull-up/Pull-down Resistors

The pin interrupts can be configured to use an internal pull-up/pull-down resistor using the associated I/O

port pull-up enable register. If an internal resistor is enabled, the PTxES register is used to select whether

the resistor is a pull-up (PTxESn = 0) or a pull-down (PTxESn = 1).

6.4.4

Pin Interrupt Initialization

When a pin interrupt is first enabled, it is possible to get a false interrupt flag. To prevent a false interrupt

request during pin interrupt initialization, the user should do the following:

1. Mask interrupts by clearing PTxIE in PTxSC.

2. Select the pin polarity by setting the appropriate PTxESn bits in PTxES.

3. If using internal pull-up/pull-down device, configure the associated pull enable bits in PTxPE.

4. Enable the interrupt pins by setting the appropriate PTxPEn bits in PTxPE.

5. Write to PTxACK in PTxSC to clear any false interrupts.

6. Set PTxIE in PTxSC to enable interrupts.

6.5

Pin Behavior in Stop Modes

Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An

explanation of pin behavior for the various stop modes follows:

•

Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as

before the STOP instruction was executed. CPU register status and the state of I/O registers should

be saved in RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon

recovery from stop2 mode, before accessing any I/O, the user should examine the state of the PPDF

bit in the SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had

occurred. If the PPDF bit is 1, I/O data previously stored in RAM, before the STOP instruction was

executed, peripherals may require being initialized and restored to their pre-stop condition. The

user must then write a 1 to the PPDACK bit in the SPMSC2 register. Access to I/O is now permitted

again in the user application program.

•

In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon

recovery, normal I/O function is available to the user.

6.6

Parallel I/O and Pin Control Registers

This section provides information about the registers associated with the parallel I/O ports. The data and

data direction registers are located in page zero of the memory map. The pull up, slew rate, drive strength,

and interrupt control registers are located in the high page section of the memory map.

Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O and their

pin control registers. This section refers to registers and control bits only by their names. A Freescale

Semiconductor-provided equate or header file normally is used to translate these names into the

appropriate absolute addresses.

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