HCS08 datasheet(80/316 Pages) NXP

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Chapter 6 Parallel Input/Output Control

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

6.6.1

Port A Registers

Port A is controlled by the registers listed below.

6.6.1.1

Port A Data Register (PTAD)

6.6.1.2

Port A Data Direction Register (PTADD)

321

PTAD3

PTAD2

PTAD1

PTAD0

Reset:

000

Figure 6-3. Port A Data Register (PTAD)

Table 6-2. PTAD Register Field Descriptions

Field

Description

5:4

Reserved

Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.

3:0

PTAD[3:0]

Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A

pins that are configured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures

all port pins as high-impedance inputs with pull-ups/pull-downs disabled.

321

PTADD3

PTADD2

PTADD1

PTADD0

Reset:

000

Figure 6-4. Port A Data Direction Register (PTADD)

Table 6-3. PTADD Register Field Descriptions

Field

Description

5:4

Reserved

Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.

3:0

PTADD[3:0]

Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for

PTAD reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.

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