HCS08 datasheet(12/316 Pages) NXP

12 / 316 page

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

Section Number

Title

Page

4.5.3 Program and Erase Command Execution .........................................................................50

4.5.4 Burst Program Execution ..................................................................................................51

4.5.5 Access Errors ....................................................................................................................53

4.5.6 FLASH Block Protection ..................................................................................................53

4.5.7 Vector Redirection ............................................................................................................54

4.6

Security ............................................................................................................................................54

4.7

FLASH Registers and Control Bits .................................................................................................55

4.7.1 FLASH Clock Divider Register (FCDIV) ........................................................................56

4.7.2 FLASH Options Register (FOPT and NVOPT) ................................................................57

4.7.3 FLASH Configuration Register (FCNFG) .......................................................................58

4.7.4 FLASH Protection Register (FPROT and NVPROT) ......................................................58

4.7.5 FLASH Status Register (FSTAT) ......................................................................................59

4.7.6 FLASH Command Register (FCMD) ...............................................................................60

Chapter 5

Resets, Interrupts, and General System Control

5.1

Introduction .....................................................................................................................................61

5.2

Features ...........................................................................................................................................61

5.3

MCU Reset ......................................................................................................................................61

5.4

Computer Operating Properly (COP) Watchdog .............................................................................62

5.5

Interrupts .........................................................................................................................................63

5.5.1 Interrupt Stack Frame .......................................................................................................64

5.5.2 Interrupt Vectors, Sources, and Local Masks ...................................................................65

5.6

Low-Voltage Detect (LVD) System ................................................................................................67

5.6.1 Power-On Reset Operation ...............................................................................................67

5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................67

5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................67

5.7

Reset, Interrupt, and System Control Registers and Control Bits ...................................................67

5.7.1 System Reset Status Register (SRS) .................................................................................68

5.7.2 System Background Debug Force Reset Register (SBDFR) ............................................69

5.7.3 System Options Register 1 (SOPT1) ................................................................................70

5.7.4 System Options Register 2 (SOPT2) ................................................................................71

5.7.5 System Device Identification Register (SDIDH, SDIDL) ................................................72

5.7.6 System Power Management Status and Control 1 Register (SPMSC1) ...........................73

5.7.7 System Power Management Status and Control 2 Register (SPMSC2) ...........................74

Chapter 6

Parallel Input/Output Control

6.1

Port Data and Data Direction ..........................................................................................................75

6.2

Pull-up, Slew Rate, and Drive Strength ..........................................................................................76

6.3

Ganged Output ................................................................................................................................77

6.4

Pin Interrupts ...................................................................................................................................78

HCS08 bảng dữ liệu(PDF) 12 Page - NXP Semiconductors

HCS08 bảng dữ liệu(HTML) 12 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL