HCS08 datasheet(90/316 Pages) NXP

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Chapter 6 Parallel Input/Output Control

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

6.6.3.5

Port C Drive Strength Selection Register (PTCDS)

6.6.3.6

Ganged Output Drive Control Register (GNGC)

321

000

PTCDS3

PTCDS2

PTCDS1

PTCDS0

Reset:

000

Figure 6-23. Drive Strength Selection for Port C Register (PTCDS)

Table 6-22. PTCDS Register Field Descriptions

Field

Description

3:0

PTCDS[3:0]

Output Drive Strength Selection for Port C Bits — Each of these control bits selects between low and high

output drive for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect.

0 Low output drive strength selected for port C bit n.

1 High output drive strength selected for port C bit n.

321

GNGPS7

GNGPS6

GNGPS5

GNGPS4

GNGPS3

GNGPS2

GNGPS1

GNGEN

Reset:

000

Figure 6-24. Ganged Output Drive Control Register (GNGC)

Table 6-23. GNGC Register Field Descriptions

Field

Description

7:1

GNGP[7:1]

Ganged Output Pin Select Bits— These write-once control bits selects whether the associated pin (see

Table 6-1for pins available) is enabled for ganged output. When GNGEN = 1, all enabled ganged output pins will

be controlled by the data, drive strength and slew rate settings for PTC0.

0 Associated pin is not part of the ganged output drive.

1 Associated pin is part of the ganged output drive. Requires GNGEN = 1.

GNGEN

Ganged Output Drive Enable Bit— This write-once control bit selects whether the ganged output drive feature

is enabled.

0 Ganged output drive disabled.

1 Ganged output drive enabled. PTC0 forced to output regardless of the value of PTCDD0 in PTCDD.

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