HCS08 datasheet(65/316 Pages) NXP

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Chapter 5 Resets, Interrupts, and General System Control

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

The status flag corresponding to the interrupt source must be acknowledged (cleared) before returning

from the ISR. Typically, the flag is cleared at the beginning of the ISR so that if another interrupt is

generated by this same source, it will be registered so it can be serviced after completion of the current ISR.

5.5.2

Interrupt Vectors, Sources, and Local Masks

Table 5-2 provides a summary of all interrupt sources. Higher-priority sources are located toward the

bottom of the table. The high-order byte of the address for the interrupt service routine is located at the

first address in the vector address column, and the low-order byte of the address for the interrupt service

routine is located at the next higher address.

When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt

enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in

the CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU

registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt.

Processing then continues in the interrupt service routine.

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