HCS08 datasheet(73/316 Pages) NXP

73 / 316 page

Chapter 5 Resets, Interrupts, and General System Control

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

5.7.6

System Power Management Status and Control 1 Register

(SPMSC1)

This high page register contains status and control bits to support the low voltage detect function, and to

enable the bandgap voltage reference for use by the ADC module.

Figure 5-8. System Power Management Status and Control 1 Register (SPMSC1)

321

RLVWF1

1 LVWF will be set in the case when V

Supply transitions below the trip point or after reset and VSupply is already below VLVW

LVWIE

LVDRE

LVDSE

LVDE

BGBE

LVWACK

Reset:

000

100

= Unimplemented or Reserved

Table 5-9. SPMSC1 Register Field Descriptions

Field

Description

LVWF

Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.

0 Low voltage warning is not present.

1 Low voltage warning is present or was present.

LVWACK

Low-Voltage Warning Acknowledge — The LVWF bit indicates the low voltage warning status.Writing a 1 to

LVWACK clears LVWF to a 0 if a low voltage warning is not present.

LVWIE

Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF.

0 Hardware interrupt disabled (use polling).

1 Request a hardware interrupt when LVWF = 1.

LVDRE

Low-Voltage Detect Reset Enable — This write-once bit enables LVD events to generate a hardware reset

(provided LVDE = 1).

0 LVD events do not generate hardware resets.

1 Force an MCU reset when an enabled low-voltage detect event occurs.

LVDSE

Low-Voltage Detect Stop Enable — Provided LVDE = 1, this control bit determines whether the low-voltage

detect function operates when the MCU is in stop mode.

0 Low-voltage detect disabled during stop mode.

1 Low-voltage detect enabled during stop mode.

LVDE

Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation

of other bits in this register.

0 LVD logic disabled.

1 LVD logic enabled.

BGBE

Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the

ADC module on one of its internal channels or ACMP on its ACMP+ input.

0 Bandgap buffer disabled.

1 Bandgap buffer enabled.

HCS08 bảng dữ liệu(PDF) 73 Page - NXP Semiconductors

HCS08 bảng dữ liệu(HTML) 73 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL