HCS08 datasheet(71/316 Pages) NXP

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Chapter 5 Resets, Interrupts, and General System Control

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

5.7.4

System Options Register 2 (SOPT2)

This high page register contains bits to configure MCU specific features on the MC9S08SG8 devices.

321

COPCLKS1

1 This bit can be written only one time after reset. Additional writes are ignored.

COPW1

ACIC

T1CH1PS

T1CH0PS

Reset:

000

= Unimplemented or Reserved

Figure 5-5. System Options Register 2 (SOPT2)

Table 5-6. SOPT2 Register Field Descriptions

Field

Description

COPCLKS

COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.

0 Internal 1-kHz clock is source to COP.

1 Bus clock is source to COP.

COPW

COP Window — This write-once bit selects the COP operation mode. When set, the 0x55-0xAA write sequence

to the SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the

first 75% of the selected period will reset the MCU.

0 Normal COP operation

1 Window COP operation (only if COPCLKS = 1)

ACIC

Analog Comparator to Input Capture Enable— This bit connects the output of ACMP to TPM1 input channel 0.

0 ACMP output not connected to TPM1 input channel 0.

1 ACMP output connected to TPM1 input channel 0.

T1CH1PS

TPM1CH1 Pin Select— This bit selects the location of the TPM1CH1 pin of the TPM1 module.

0 TPM1CH1 on PTB5.

1 TPM1CH1 on PTC1.

T1CH0PS

TPM1CH0 Pin Select— This bit selects the location of the TPM1CH0 pin of the TPM1 module.

0 TPM1CH0 on PTA0.

1 TPM1CH0 on PTC0.

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