HCS08 datasheet(172/316 Pages) NXP

172 / 316 page

Inter-Integrated Circuit (S08IICV2)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

172

Freescale Semiconductor

11.4.1.2

Slave Address Transmission

The first byte of data transferred immediately after the start signal is the slave address transmitted by the

master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired

direction of data transfer.

1 = Read transfer, the slave transmits data to the master.

0 = Write transfer, the master transmits data to the slave.

Only the slave with a calling address that matches the one transmitted by the master responds by sending

back an acknowledge bit. This is done by pulling the SDA low at the ninth clock (see Figure 11-9).

No two slaves in the system may have the same address. If the IIC module is the master, it must not

transmit an address equal to its own slave address. The IIC cannot be master and slave at the same time.

However, if arbitration is lost during an address cycle, the IIC reverts to slave mode and operates correctly

even if it is being addressed by another master.

11.4.1.3

Data Transfer

Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction

specified by the R/W bit sent by the calling master.

All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address

information for the slave device

Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while

SCL is high as shown in Figure 11-9. There is one clock pulse on SCL for each data bit, the msb being

transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the

receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary, one

complete data transfer needs nine clock pulses.

If the slave receiver does not acknowledge the master in the ninth bit time, the SDA line must be left high

by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer.

If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave

interprets this as an end of data transfer and releases the SDA line.

In either case, the data transfer is aborted and the master does one of two things:

•

Relinquishes the bus by generating a stop signal.

•

Commences a new calling by generating a repeated start signal.

11.4.1.4

Stop Signal

The master can terminate the communication by generating a stop signal to free the bus. However, the

master may generate a start signal followed by a calling command without generating a stop signal first.

This is called repeated start. A stop signal is defined as a low-to-high transition of SDA while SCL at

logical 1 (see Figure 11-9).

The master can generate a stop even if the slave has generated an acknowledge at which point the slave

must release the bus.

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