HCS08 datasheet(171/316 Pages) NXP

171 / 316 page

Inter-Integrated Circuit (S08IICV2)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

171

11.4

Functional Description

This section provides a complete functional description of the IIC module.

11.4.1

IIC Protocol

The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices

connected to it must have open drain or open collector outputs. A logic AND function is exercised on both

lines with external pullup resistors. The value of these resistors is system dependent.

Normally, a standard communication is composed of four parts:

•

Start signal

•

Slave address transmission

•

Data transfer

•

Stop signal

The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication

is described briefly in the following sections and illustrated in Figure 11-9.

Figure 11-9. IIC Bus Transmission Signals

11.4.1.1

Start Signal

When the bus is free, no master device is engaging the bus (SCL and SDA lines are at logical high), a

master may initiate communication by sending a start signal. As shown in Figure 11-9, a start signal is

defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new

data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle

states.

SCL

SDA

Start

Signal

Ack

Bit

4567

msb

lsb

4567

msb

lsb

Stop

Signal

SCL

SDA

456

msb

lsb

msb

lsb

Repeated

AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W

XXX

Calling Address

Read/

Data Byte

AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W

New Calling Address

Ack

Bit

Write

Start

Signal

Start

Signal

Ack

Bit

Calling Address

Read/

Write

Stop

Signal

Ack

Bit

Read/

Write

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