HCS08 datasheet(170/316 Pages) NXP

170 / 316 page

Inter-Integrated Circuit (S08IICV2)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

170

Freescale Semiconductor

NOTE

When transitioning out of master receive mode, the IIC mode should be

switched before reading the IICD register to prevent an inadvertent

initiation of a master receive data transfer.

In slave mode, the same functions are available after an address match has occurred.

The TX bit in IICC must correctly reflect the desired direction of transfer in master and slave modes for

the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is

desired, reading the IICD does not initiate the receive.

Reading the IICD returns the last byte received while the IIC is configured in master receive or slave

receive modes. The IICD does not reflect every byte transmitted on the IIC bus, nor can software verify

that a byte has been written to the IICD correctly by reading it back.

In master transmit mode, the first byte of data written to IICD following assertion of MST is used for the

address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required

R/W bit (in position bit 0).

11.3.6

IIC Control Register 2 (IICC2)

Table 11-8. IICD Field Descriptions

Field

Description

7–0

DATA

Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant

bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.

321

GCAEN

ADEXT

AD10

AD9

AD8

Reset

000

= Unimplemented or Reserved

Figure 11-8. IIC Control Register (IICC2)

Table 11-9. IICC2 Field Descriptions

Field

Description

GCAEN

General Call Address Enable. The GCAEN bit enables or disables general call address.

0 General call address is disabled

1 General call address is enabled

ADEXT

Address Extension. The ADEXT bit controls the number of bits used for the slave address.

0 7-bit address scheme

1 10-bit address scheme

2–0

AD[10:8]

Slave Address. The AD[10:8] field contains the upper three bits of the slave address in the 10-bit address

scheme. This field is only valid when the ADEXT bit is set.

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