HCS08 datasheet(328/374 Pages) NXP

328 / 374 page

Development Support

MC9S08JM60 Series Data Sheet, Rev. 5

328

Freescale Semiconductor

When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD

chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU

into active background mode after reset. The specific conditions for forcing active background depend

upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not

necessary to reset the target MCU to communicate with it through the background debug interface.

18.2.2

Communication Details

The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to

indicate the start of each bit time. The external controller provides this falling edge whether data is

transmitted or received.

BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data

is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if

512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress

when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU

system.

The custom serial protocol requires the debug pod to know the target BDC communication clock speed.

The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the

BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source.

The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams

show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but

asynchronous to the external host. The internal BDC clock signal is shown for reference in counting

cycles.

HCS08 bảng dữ liệu(PDF) 328 Page - NXP Semiconductors