HCS08 datasheet(190/374 Pages) NXP

190 / 374 page

Multi-Purpose Clock Generator (S08MCGV1)

MC9S08JM60 Series Data Sheet, Rev. 5

190

Freescale Semiconductor

12.4

Functional Description

12.4.1

Operational Modes

Figure 12-8. Clock Switching Modes

The nine states of the MCG are shown as a state diagram and are described below. The arrows indicate the

allowed movements between the states.

12.4.1.1

FLL Engaged Internal (FEI)

FLL engaged internal (FEI) is the default mode of operation and is entered when all the following

conditions occur:

•

CLKS bits are written to 00

•

IREFS bit is written to 1

•

PLLS bit is written to 0

•

RDIV bits are written to 000. Since the internal reference clock frequency should already be in the

range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary.

Entered from any state

when MCU enters stop

Returns to state that was active

before MCU entered stop, unless

RESET occurs while in stop.

Stop

PLL Bypassed

External (PBE)

PLL Engaged

External (PEE)

FLL Engaged

External (FEE)

FLL Engaged

Internal (FEI)

FLL Bypassed

External (FBE)

FLL Bypassed

Internal (FBI)

IREFS=1

CLKS=00

PLLS=0

IREFS=0

CLKS=00

PLLS=0

IREFS=1

CLKS=01

PLLS=0

IREFS=0

CLKS=10

PLLS=0

IREFS=0

CLKS=00

PLLS=1

IREFS=0

CLKS=10

PLLS=1

IREFS=0

CLKS=10

BDM Disabled

and LP=1

IREFS=1

CLKS=01

BDM Disabled

and LP=1

Bypassed

Low Power

Internal (BLPI)

Bypassed

Low Power

External (BLPE)

BDM Enabled

or LP=0

BDM Enabled

or LP=0

BDM Enabled

or LP=0

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