HCS08 datasheet(185/374 Pages) NXP

185 / 374 page

Multi-Purpose Clock Generator (S08MCGV1)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

185

12.3.2

MCG Control Register 2 (MCGC2)

432

BDIV

RANGE

HGO

EREFS

ERCLKEN

EREFSTEN

Reset:

000

Figure 12-4. MCG Control Register 2 (MCGC2)

Table 12-2. MCG Control Register 2 Field Descriptions

Field

Description

7:6

BDIV

Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits in the

MCGC1 register. This controls the bus frequency.

Encoding 0 — Divides selected clock by 1

Encoding 1 — Divides selected clock by 2 (reset default)

Encoding 2 — Divides selected clock by 4

Encoding 3 — Divides selected clock by 8

RANGE

Frequency Range Select — Selects the frequency range for the external oscillator or external clock source.

1 High frequency range selected for the external oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external

clock source)

0 Low frequency range selected for the external oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external

clock source)

HGO

High Gain Oscillator Select — Controls the external oscillator mode of operation.

1 Configure external oscillator for high gain operation

0 Configure external oscillator for low power operation

Low Power Select — Controls whether the FLL (or PLL) is disabled in bypassed modes.

1 FLL (or PLL) is disabled in bypass modes (lower power)

0 FLL (or PLL) is not disabled in bypass modes.

EREFS

External Reference Select — Selects the source for the external reference clock.

1 Oscillator requested

0 External Clock Source requested

ERCLKEN

External Reference Enable — Enables the external reference clock for use as MCGERCLK.

1 MCGERCLK active

0 MCGERCLK inactive

EREFSTEN

External Reference Stop Enable — Controls whether or not the external reference clock remains enabled when

the MCG enters stop mode.

1 External reference clock stays enabled in stop if ERCLKEN is set or if MCG is in FEE, FBE, PEE, PBE, or

BLPE mode before entering stop

0 External reference clock is disabled in stop

HCS08 bảng dữ liệu(PDF) 185 Page - NXP Semiconductors

HCS08 bảng dữ liệu(HTML) 185 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL