HCS08 datasheet(184/374 Pages) NXP

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Multi-Purpose Clock Generator (S08MCGV1)

MC9S08JM60 Series Data Sheet, Rev. 5

184

Freescale Semiconductor

12.3

12.3.1

MCG Control Register 1 (MCGC1)

432

CLKS

RDIV

IREFS

IRCLKEN

IREFSTEN

Reset:

Figure 12-3. MCG Control Register 1 (MCGC1)

Table 12-1. MCG Control Register 1 Field Descriptions

Field

Description

7:6

CLKS

Clock Source Select — Selects the system clock source.

Encoding 0 — Output of FLL or PLL is selected.

Encoding 1 — Internal reference clock is selected.

Encoding 2 — External reference clock is selected.

Encoding 3 — Reserved, defaults to 00.

5:3

RDIV

Reference Divider — Selects the amount to divide down the reference clock selected by the IREFS bit. If the

FLL is selected, the resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. If the PLL is selected,

the resulting frequency must be in the range 1 MHz to 2 MHz.

000 Encoding 0 — Divides reference clock by 1 (reset default)

001 Encoding 1 — Divides reference clock by 2

010 Encoding 2 — Divides reference clock by 4

011 Encoding 3 — Divides reference clock by 8

100 Encoding 4 — Divides reference clock by 16

101 Encoding 5 — Divides reference clock by 32

110 Encoding 6 — Divides reference clock by 64

111 Encoding 7 — Divides reference clock by 128

IREFS

Internal Reference Select — Selects the reference clock source.

1 Internal reference clock selected

0 External reference clock selected

IRCLKEN

Internal Reference Clock Enable — Enables the internal reference clock for use as MCGIRCLK.

1 MCGIRCLK active

0 MCGIRCLK inactive

IREFSTEN

Internal Reference Stop Enable — Controls whether or not the internal reference clock remains enabled when

the MCG enters stop mode.

1 Internal reference clock stays enabled in stop if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI mode before

entering stop

0 Internal reference clock is disabled in stop

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