AD4884BBCZ datasheet(27/116 Pages) AD

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Data Sheet

AD4884

THEORY OF OPERATION

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PRODUCT OVERVIEW

The AD4884 is a dual-channel, 16-bit, 20MSPS per channel, SAR

ADC with integrated fully-differential drivers. It is built as a system

in package (SiP) that contains four separate die (two ADCs and

two FDAs) along with gain-setting resistors and critical decoupling

capacitors. In-package integrated components minimize the overall

solution area, reduce the potential performance errors introduced

by factors such as component selection, placement and routing

challenges, and in general reduce the engineering effort to first

design success.

The combination of a state-of-the-art ADC with a low-noise FDA

enables reaching typical SNR figures as high as 91.9dB, result

output latency of 78.13ns, and high signal fidelity for signals up

to 1MHz. This parametric performance, throughput, and bandwidth

make this product ideal for a variety of high-speed, data-acquisition

applications. Accounting for its low power consumption, the product

becomes an exceptionally apt choice for applications where chan-

nel density and thermal management present a challenge.

The external selection of the gain-setting resistors allows choosing

the gain among a set of prefixed values, while the ability to place

additional capacitors facilitates bandwidth adjustment. The FDAs

can accommodate single-ended or differential input signals, do

not require external generation of a common-mode voltage, and

generally remove common SAR ADC drive challenges such as

PCB layout, kickback settling calculations, and output filter design.

The SiP approach results in complete independence in channel

configuration and data access. For each channel, conversion result

access occurs via one of its two independent data interfaces: its

multilane LVDS port operating at clock rates up to 160MHz or via its

multioutput SPI operating at clock rates up to 50MHz.

A rich digital feature set increases the flexibility of the device

and can potentially simplify system complexity and reduce the

load on the digital host. These features include a 16,384 sample

FIFO memory per channel, internal and external event detection,

multifunction GPIOs, digital filtering, and system error correction

coefficients.

TRANSFER FUNCTION

Each AD4884 channel digitizes the full-scale difference voltage at

the input of the SAR ADC of 2 × VREFIN into 216 levels, resulting in

an LSB size of 91.55μV with VREFIN = 3.0V. Note that 1 LSB at 16

bits is approximately 15.26ppm. Note also that the transfer function

is defined at input of the ADC, not the INx±ChX pins at the input of

the AFE. The polarity is preserved in the sense that a positive value

for INx+ChX − INx−ChX results in a positive voltage measurement.

Table 7 summarizes the mapping of input voltages to differential

output codes.

Figure 49. ADC Ideal Transfer Function for the Differential Output Codes

(FSR is Full-Scale Range)

Table 7. Input Voltage to Output Code Mapping

Description

ADC Analog Input Voltage

Difference (Volts)

Digital Output Code (Twos

Complement, Hex)

FS − 1 LSB

+VREFIN × (1 − 1/215)

0x7FFF

Midscale + 1 LSB +VREFIN/215

0x0001

Midscale

0x0000

Midscale − 1 LSB −VREFIN/215

0xFFFF

−FS + 1 LSB

−VREFIN × (1 − 1/215)

0x8001

−FS

−VREFIN

0x8000

REFERENCE BUFFER AND COMMON-MODE

OUTPUT

The AD4884 requires an external 3.0V reference to drive the

REFIN pin. The REFIN pin integrates a capacitor array totaling

18.8μF ± 20%. The capacitor array is constructed from commercial-

ly available, multilayer, high dielectric (X6S), ceramic capacitors,

and it serves as the primary charge reservoir, which is shared by

the two SAR ADCs.

Additional external capacitance (CRSV) can optionally be placed

across the REFIN and REFGND pins for improved charge capacity

and noise rejection, as required. As with all precision circuits, the

placement of the external reference capacitors must be as close

to the device pins as possible on the same side of the PCB. The

routing between the capacitor and device pins must minimize the

series impedance in each routing path.

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