AD4884BBCZ datasheet(88/116 Pages) AD

88 / 116 page

Data Sheet

AD4884

DIGITAL FEATURES

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Rev. 0 | 88 of 116

Filter Result Ready Indicator

Setting the GPIO_x_SEL bits to 0011 configures the GPIO to output

the FILTER_RESULT_RDY signal, which is an active low logic

signal that indicates to the host controller when each new filter

result from the channel is complete. When LVDS is used to directly

read out the filter results, this indicator can alert the user when each

new filtered conversion result is available to read via the interface.

Filter Interface Timing Considerations

Continuous access to filtered data results of a channel is available

only through its LVDS data interface. SPI data interface access

to filtered results is only made via the FIFO. The timing consider-

ations, in this case, are described in the Filter Interface Timing

Considerations when Using the FIFO section. For use with the

LVDS data interface, it is recommended to use a GPIO, configured

with the appropriate GPIO_x_SEL (0011) to output the filter result

ready (active low) signal, as shown in the example Figure 133

timing diagram.

Filter Interface Timing Considerations when

Using the FIFO

Figure 135 serves as an example to show the sequence of events

in this mode of operation. This example shows a sinc1 filter with a

decimate by 2 setting, where three results (that is, WATERMARK

= 3) are configured to be stored in the FIFO. When using the

integrated digital filters with the FIFO, the filter must be reset prior

to each FIFO acquisition record. This reset must be given on the

first CNVChX rising edge, where the FILTER_SYNC signal must

be brought low at least 15ns prior to the CNVChX edge and then

released at least 5ns before the next rising edge. The first ADC

result is ready tMSB after the second CNVChX rising edge. This first

ADC result is latched into the filter on the third CNVChX rising edge.

The fourth CNVChX rising edge latches the second ADC result into

the digital filter. On the fifth rising edge, the first decimate by 2

result is complete, which is indicated by the FILTER_READY signal

going active on the fifth rising edge. This first filtered result is

loaded into the FIFO on the sixth CNVChX rising edge. Because

this example uses WATERMARK = 3, when three filtered (that is,

six core ADC results, decimated by 2) results are loaded to the

FIFO, the WATERMARK is reached, and FIFO_FULL is asserted

to indicate to the user that a FIFO record is available to read via

the configured data interface (that is, the LVDS data lane(s) of the

SPI data lane(s)). To initiate a subsequent FIFO record acquisition

of the filtered ADC results, the user must start the whole sequence

over, beginning again with the reset of the digital filter by bringing

the FILTER_SYNC signal low on the first rising edge of CNVChX.

Figure 135. Description of Filter Timing with FIFO

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