AD4884BBCZ datasheet(48/116 Pages) AD

48 / 116 page

Data Sheet

AD4884

DIGITAL INTERFACE

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Rev. 0 | 48 of 116

OVERVIEW

The system-in-package construction of AD4884, with two separate

ADC die, results in a fully-independent digital interface for each

channel. Each digital interface consists of a 4-wire SPI for de-

vice configuration, four general-purpose input and output (GPIO)

pins, a conversion data access interface with selectable output

format (LVDS or SPI data interface), and a conversion start input

(CNV+ChX and CNV−ChX) that can be configured for LVDS or

CMOS level signaling.

Each AD4884 channel has its own separate configuration memory.

The configuration registers of each channel are accessed through

the corresponding SPI configuration interface (see the SPI Configu-

ration Interface section).

ADC Conversion Control

The ADC conversions of each AD4884 channel can be independ-

ently controlled. Each ADC acquires a sample and initiates a

conversion operation on the rising edge of a convert start signal,

applied at its CNV+ChX and CNV−ChX pins. Due to both channels

being identical, AD4884 is also apt for simultaneous sampling

applications (see the examples in Data Interface Clocking Solution

section).

The input stages of the ADCs inside AD4884 cannot stay indefi-

nitely in acquisition mode. This means that there is a minimum

sampling frequency that must be exercised (see Timing Specifica-

tions), and that the first two samples acquired after power up or

after a sleep or standby period are not guaranteed to be correct,

and hence must be discarded.

There are two possible configurations for the electrical signaling

at the convert start input pins CNV±ChX: CMOS or LVDS. CMOS

is the default mode on power up and after reset. CMOS requires

that the CNV−ChX pin be connected to the digital interface ground

(IOGND). In this mode, the convert signal must be a CMOS logic

signal referenced to IOGND and applied at CNV+ChX, with logic

levels according to the digital inputs (CNVChX, GPIOxChX, DCSChX,

and DCLKChX) parameters in Table 1.

To switch a channel to LVDS mode, the LVDS_CNV_EN bit of its

ADC Data Interface Configuration B register (see the ADC Data

Interface Configuration B Register section, Address 0x16) must

be set to 1. In this mode, an external 100Ω termination resistor

must be installed between the CNV+ChX and CNV−ChX pins, as

close to the AD4884 as possible. In LVDS mode, the CNV+ChX

and CNV−ChX pins must be driven differentially with an LVDS

driver conforming to the levels specified in the LVDS I/O (EIA-644)

parameters in Table 1. A user must take care to closely match the

CNV+ChX and CNV−ChX differential signal pair routing and to use

controlled impedance to ensure signal integrity. If the application

aims at simultaneous sampling for both channels, proper fanning-

out of the common conversion clock must be implemented, along

with path length matching also between the CNV±ChA and CNV±ChB

signal pairs.

ADC Conversion Data Interface

The ADC conversion data interface of each channel can be inde-

pendently configured to one of the following signaling options:

►

LVDS level signaling (LVDS data Interface)

►

CMOS level signaling (SPI data interface)

The choice of interface is usually determined by the requirements

and constraints of the application at hand. For example, if contin-

uous fast data acquisition is required, then the LVDS signaling

interface is typically the preferred option. If the application requires

only noncontinuous bursts of data acquisitions, then either the

LVDS or the SPI data interfaces can be used. The capabilities of

the digital interface host can also determine which interface option

is chosen.

Common to both the LVDS and SPI data interfaces are the follow-

ing flexible features, which reduce the burden on the chosen digital

host:

►

Multilane data transfer: enables sustained data throughput at

reduced interface clock speeds.

►

Test pattern generation: facilitates interface integrity checks.

Additionally, for the LVDS only, there is the option to set a configu-

rable output drive.

By default, the LVDS interface is selected on power up and after a

reset. As shown in Figure 87, for LVDS, the data path of the ADC

results is routed though the offset and gain correction block where

there is the option to:

►

Continuously read, directly, the raw ADC conversion results.

►

Continuously read the ADC results processed by a user-selected

digital filter (for more details, see the Digital Filter section).

►

Read up to 16k unfiltered results from the channel FIFO.

►

Read up to 16k digitally filtered results from the channel FIFO.

Figure 87. LVDS Data Interface Options (Shown for One Channel)

If configured for the SPI data interface, as shown in Figure 88, the

available data paths are as follows:

►

Read up to 16k unfiltered results from the channel FIFO.

►

Read up to 16k digitally filtered results from the channel FIFO.

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