AD4884BBCZ datasheet(92/116 Pages) AD

92 / 116 page

Data Sheet

AD4884

LAYOUT GUIDELINES

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Rev. 0 | 92 of 116

The AD4884 includes all critical bypass capacitors within the device

package, which along with the integration of the FDAs greatly

reduces the layout challenge for a precision, high-speed converter.

The integrated capacitors are optimally placed within the device

package to ensure that maximum performance is easily obtained.

However, as with any precision mixed signal device, a user must

take care in system device placement to ensure that there is proper

partitioning of the critical analog signal chain component routing

and routing of the high-speed digital signals to prevent unwanted

coupling effects.

Note the following layout considerations:

►

The summing junction pins (SJ±ChX) and output pins (OUT±ChX)

of the FDA must be treated carefully because of their sensitivity.

Most applications will benefit from restricting the bandwidth of the

FDA by the placement of external capacitors (Cfb) across these

pins, in parallel to the internal 2.7pF ones. These capacitors

must be placed on the bottom layer right below the connection

points to minimize trace inductance, as even relatively small

parasitics can potentially degrade the characteristics of the FDA.

Unnecessary trace stubs should be avoided for these sensitive

nodes.

►

The AD4884 contains internal decoupling on all power supplies,

AVDD33 (0.47μF), VDD11ChA and VDD11ChB (1.88μF each),

IOVDDChA and IOVDDChB(0.22μF each), VDDLDO (0.22μF), +VS

(0.44μF) and −VS (0.44μF). Therefore, no external bypass ca-

pacitors are required, saving board space and reducing bill of

material (BOM) count and sensitivity.

►

Ensure good partitioning of analog and digital domain signals

within the design by, for example, having all analog signals in

from the left-hand side and keeping dynamic digital signals on

the right-hand side.

►

Have a solid ground plane under the AD4884 and connect all

analog ground (GND) pins, reference ground (REFGND), and

digital ground (IOGND) pins to this shared plane.

►

Recommended connections of ground (GND), reference ground

(REFGND), and digital ground (IOGND) connections are shown

in Figure 144. It is recommended not to keep the current return

path of the reference IC in the same current loop as the current

return loop from other circuitry on the PCB. Connect the refer-

ence local star point to the ADC star point ground on the top

layer of the PCB, as shown in Figure 144.

►

For the side view cross-section of the PCB board showing the

ground planes distribution, see Figure 145. Note that Figure 145

only shows the ground planes but does not include the signal

tracks.

Figure 144. AD4884 External Reference Ground Connections

Figure 145. Recommended PCB Ground Planes Layout

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