AD4884BBCZ datasheet(45/116 Pages) AD

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Data Sheet

AD4884

APPLICATIONS INFORMATION

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Rev. 0 | 45 of 116

REFERENCE CIRCUITRY DESIGN

The AD4884 requires a low noise, high precision and stability,

and low temperature drift external reference of 3V. The internal

buffers allow the same reference to be used for both channels.

This reference defines a differential input range at the input of the

SAR ADCs of ±VREFIN. The reference must be within ±5mV of +3V.

Recommended references are LTC6655, LT6657, or ADR4530. For

best performance, however, use the LTC6655 external reference.

Table 13 details the typical parameters of the previously mentioned

references, comparing absolute accuracy, noise, temperature drift,

load regulation, and power consumption. For more detailed specifi-

cations, refer to the data sheet of the given product.

Table 13. Comparison of the Main Parameters of the LTC6655, LT6657, and

ADR4530 References

Parameter

LTC6655

LT6657

ADR4530B

Accuracy

0.025%

0.1%

0.02%

Temperature Coefficient

(ppm/°C)

1.5

0.1Hz to 10Hz Noise (ppm p-p) 0.25

0.5

0.53

Maximum Load (mA)

±5

±10

Load Regulation (ppm/mA)

0.7

Maximum Supply (V)

13.2

Shutdown

Yes

Supply Current, IS (mA)

1.2

0.7

There is no need for the external reference capacitor because

the AD4884 embeds internally a total of 18.8μF at the REFIN pin

(9.4μF per channel, see Figure 82). The REFIN reference input pin

is internally buffered, which substantially reduces ADC conversion

transients and isolates the external reference from these transients.

Therefore, no external amplifier is required to buffer the external

reference. For the reference input capacitance (CREF IN) and ref-

erence output capacitance (CREF OUT) values, refer to the given

external reference IC data sheet recommendations. As a layout

recommendation, the external reference chip must be placed as

close as possible to the AD4884 and its REFIN pinto minimize

the series impedance of the track connecting the REFIN pin to

the external reference output. It is recommended to minimize the

exposure of this track to noisy signals, especially digital ones.

Figure 82. AD4884 General External Reference Design Functional Diagram

DATA INTERFACE CLOCKING SOLUTION

Each AD4884 channel has its own independent LVDS data inter-

face. When designing the LVDS data interfaces (see the LVDS

Data Interface section), the user must ensure the clocking solution

adheres to the timing specifications of the AD4884 (see Table 2).

When configured for LVDS mode data interface, the user must en-

sure that timing specifications stay within the maximum conversion

to clock alignment time of ±535ps (tCCA). In addition, ensure that

a low jitter conversion (CNV) clock is provided such that there

is no unwanted impact to SNR performance. This jitter is signal

frequency dependent, therefore, the level of jitter tolerable in a

given system is dependent on the application use case. For more

details on this topic, refer to the technical article Maximum SNR vs

Clock Jitter.

As an example, Figure 83 shows a recommended clocking solution

where both AD4884 channels are configured to use the LVDS data

interface with a single lane enabled and using echo clock mode. In

this solution, a 25MHz oscillator is selected with low phase noise

and jitter. Tutorial MT-008 serves as an aid to convert between

phase noise and RMS phase jitter, often quoted interchangeably

in crystal oscillator product data sheets. The ADF4350 wideband

synthesizer with an integrated voltage-controlled oscillator (VCO)

serves as versatile means of generating a 160MHz system clock,

while maintaining low jitter and offering flexibility and control to

reconfigure this frequency depending on the application needs. This

clock then feeds the AD9508 clock fanout buffer with output divid-

ers, that can be configured for the desired LVDS level signaling.

As shown in Figure 83, two output channels are set to divide by

1 to generate the LVDS clocks (CLK±ChA, CLK±ChB), while two

other output channels are configured to divide by 8, to generate the

AD4884 conversion clocks (CNV±ChA, CNV±ChB). This 1:8 ratio of

CNV:CLK frequencies ensures 16 bits of data can be read out over

the double data rate (DDR), single lane, LVDS data interface. For

a dual lane configuration, such as shown in Figure 84, this ratio is

adjusted to 1:4.

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