AD4884BBCZ datasheet(64/116 Pages) AD

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Data Sheet

AD4884

DIGITAL INTERFACE

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Rev. 0 | 64 of 116

Echo Clock Mode

In LVDS data interface mode, the DCO+ChX and DCO−ChX pin

pair is an echo clock output that provides a buffered and de-

layed version of CLK+ChX and CLK−ChX pin pair, facilitating data

clocking to the host controller. This feature is controlled by the

LVDS_SELF_CLK_MODE bit in the ADC Data Interface Configura-

tion B register (see the ADC Data Interface Configuration B Regis-

ter section, Address 0x16). By default, echo clock mode is active

(LVDS_SELF_CLK_MODE = 0). Setting LVDS_SELF_CLK_MODE

= 1 disables the DCO+ChX and DCO−ChX output driver, putting the

device in self clock mode (see the Self Clock Mode section) .

When echo clock mode is active, the interface requires a mini-

mum of three LVDS pairs (CLK+ChX and CLK−ChX, DCO+ChX and

DCO−ChX, and DA+ChX and DA−ChX) to be connected between the

host controller and the AD4884. A maximum of five LVDS pairs

are required if the CNV+ChX and CNV−ChX pin pair is configured

as an LVDS input and the DB+ChX and DB−ChX data lane is

enabled. The conversion clock (CNV+ChX and CNV−ChX) and data

clock (CLK+ChX and CLK−ChX) can be shared amongst channels

or multiple AD4884 devices as long as care is taken to fanout

the clock network, such that the edge placement requirement is

satisfied.

In echo clock mode, data from enabled lanes is clocked out in

sync to both rising and falling edges of DCO+ChX and DCO−ChX

in a DDR scheme. Figure 110 and Figure 111 show the relevant

LVDS interface timing with respect to the DCO+ChX and DCO−ChX

echo clock for single and dual lane configurations, respectively.

Calculation of tMSB_READ is described in the ADC Result Latency

and LVDS Interface Alignment section.

Consider matching the data clock (DCO+ChX and DCO−ChX) and

data lane (DA+ChX and DA−ChX, DB+ChX and DB−ChX) lane routing

from the ADC to the host processor for the physical layout to mini-

mize timing skew, which may affect data recovery in the host. For

additional routing suggestions, see the Layout Guidelines section.

Figure 110. Continuous Conversion Timing, LVDS Data Interface, Single Data Lane, Echo Clock Mode

Figure 111. Continuous Conversion Timing, LVDS Data Interface, Dual Data Lane, Echo Clock Mode

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