AD4884BBCZ datasheet(49/116 Pages) AD

49 / 116 page

Data Sheet

AD4884

DIGITAL INTERFACE

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Rev. 0 | 49 of 116

Figure 88. SPI Data Interface Data Path Options (Shown for One Channel)

Additional features specific to the selected interface format are also

available and are described in the LVDS Data Interface and the SPI

Data Interface sections.

SPI CONFIGURATION INTERFACE

All serial transactions between the system host and each AD4884

channel configuration registers are executed using their respective

configuration SPI interfaces. Each serial transaction consists of

at least one instruction phase during which the desired memory

operation, that is, read or write, and the starting address for the

transaction are transmitted to the AD4884 channel. The instruction

phase is immediately followed by a data transaction phase during

which one or more bytes of information is exchanged between

the host and the AD4884 channel. This content is framed by a

continuous assertion of the interface chip select ( CSChX ) as shown

in the generic timing presented in Figure 89 and Figure 90.

Figure 89. Generic SPI Configuration Frame, CRC Disabled

Figure 90. Generic SPI Configuration Write Operation, CRC Enabled

SPI Register Interface

Each AD4884 channel has its own independent configuration regis-

ter interface in the form of an SPI that enables both configuration

and status monitoring. Each interface is configured for 4-wire,

full-duplex operation. Dedicated interface pins for the interface

chip select (CSChX), serial clock (SCLKChX), and serial data input

(SDIChX) are intended for direct connection to the host controller.

By default, at power-up or after a software reset, the configuration

interface SDO function is enabled and assigned to the GPIO0ChX

pin.

The configuration interface timing convention is consistent with SPI

Mode 3 (clock polarity CPOL = 1, clock phase CPHA = 1). As such,

the serial clock (SCLKChX) is expected to idle high and the state

of the data pins, SDIChX and SDOChX, are updated on the falling

(leading) edge of the clock such that these pin can be sampled

on the subsequent rising (trailing) edge. For more details regarding

the SPI and SPI modes, refer to the Introduction to SPI Interface

article .

Each memory access controller associated with the SPI register

interfaces supports a number of user-programmable options acces-

sible through its respective interface configuration memory space

(Address 0x00 to Address 0x11). The available options are listed

and described in Table 14.

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