AD4884BBCZ datasheet(16/116 Pages) AD

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Data Sheet

AD4884

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. 0 | 16 of 116

Table 6. Pin Function Descriptions (Continued)

Pin Number

Mnemonic

Type1

Description

GPIO3ChB

DI/O

Channel B ADC General-Purpose Input and Output 3 Pin.

DCO−ChB

Channel B ADC LVDS Echo Clock Negative Output.

This output pin, along with DCO+ChB, outputs a buffered and delayed version of CLK+ChB and CLK−ChB.

Data outputs from LVDS Data Lanes (DA±ChB and DB±ChB, if active) are clocked out in alignment with

both rising and falling edges of DCO+ChB and DCO−ChB. If the echo clock mode is disabled, these pins

can be left unconnected.

DB+ChB/SDOCChB

Channel B ADC Data Interface Output Multifunction Pin.

In LVDS data interface mode (default), this output pin along with DB−ChB serves as the optional,

secondary LVDS Data Lane B for the ADC. If unused, leave unconnected.

When the ADC is in SPI data interface mode, this pin functions as Serial Data Output C (SDOCChB),

which is active in a 4-lane configuration only. Result data is shifted out of this pin on the falling edge of the

data interface clock (DCLKChB).

This pin must left unconnected if not being used.

DB−ChB/SDODChB

Channel B ADC Data Interface Output Multifunction Pin.

When the ADC is in LVDS data interface mode (default), this output pin along with DB+ChB serves as the

optional, secondary LVDS Data Lane B. If unused, leave unconnected.

When the ADC is in SPI data interface mode, this pin functions as Serial Data Output D (SDODChB),

which is active in a 4-lane configuration only. Result data is shifted out of this pin on the falling edge of the

data interface clock (DCLKChB). Note that this pin does not go into a high impedance state when used in

4-lane SPI mode when DCSChB is high.

This pin must be left unconnected if not being used.

GPIO0ChA

DI/O

Channel A ADC General-Purpose Input and Output 0 Pin.

By default, this pin is enabled as an output and functioning as Channel A Configuration SPI SDO.

GPIO1ChA

DI/O

Channel A ADC General-Purpose Input and Output 1 Pin.

N10

GPIO2ChA

DI/O

Channel A ADC General-Purpose Input and Output 2 Pin.

N11

GPIO3ChA

DI/O

Channel A ADC General-Purpose Input and Output 3 Pin.

N12

DCO−ChA

Channel A ADC LVDS Echo Clock Negative Output.

This pin, along with DCO+ChA, outputs a buffered and delayed version of CLK+ChA and CLK−ChA. Data

outputs from LVDS Data Lanes (DA±ChA and DB±ChA, if active) are clocked out in alignment with both

rising and falling edges of DCO+ChA and DCO−ChA. If the echo clock mode is disabled, these pins can be

left unconnected.

N13

DB+ChA/SDOCChA

Channel A ADC Data Interface Output Multifunction Pin.

In LVDS data interface mode (default), this output pin along with DB−ChA serves as the optional,

secondary LVDS Data Lane B for the ADC. If unused, leave unconnected.

When the ADC is in SPI data interface mode, this pin functions as Serial Data Output C (SDOCChA),

which is active in a 4-lane configuration only. Result data is shifted out of this pin on the falling edge of the

data interface clock (DCLKChA).

This pin must left unconnected if not being used.

N14

DB−ChA/SDODChA

Channel A ADC Data Interface Output Multifunction Pin.

When the ADC is in LVDS data interface mode (default), this output pin along with DB+ChA serves as the

optional, secondary LVDS Data Lane B. If unused, leave unconnected.

When the ADC is in SPI data interface mode, this pin functions as Serial Data Output D (SDODChA),

which is active in a 4-lane configuration only. Result data is shifted out of this pin on the falling edge of the

data interface clock (DCLKChA). Note that this pin does not go into a high impedance state when used in

4-lane SPI mode when DCSChA is high.

This pin must be left unconnected if not being used.

SCLKChB

Channel B ADC Configuration Interface Serial Data Clock. This clock input is used to shift data into and

out of the device configuration memory.

SDIChB

Channel B ADC Configuration Interface Serial Data Input. Data is shifted into this input on the rising edge

of the serial data clock, SCLKChB.

CS ChB

Channel B ADC Configuration Interface Chip-Select Input (Active Low). The CSChB input frames serial

data transfers over the Configuration SPI.

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