AD4884BBCZ datasheet(28/116 Pages) AD

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Data Sheet

AD4884

THEORY OF OPERATION

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Rev. 0 | 28 of 116

Figure 50. REFIN and CMO Internal Equivalent Circuit and Typical

Application

Each AD4884 channel internally generates a common-mode ref-

erence voltage of one-half of VREFIN, they are output through

the CMOChX pins. The CMOChX outputs are used to set the com-

mon-mode output voltage of their respective analog front-ends. To

achieve this, each CMOChX output must be directly connected to

its corresponding VOCM_ChX and decoupled with a recommended

capacitance of 100nF.

Each CMOChX output is generated using a resistive divider connect-

ed to the reference buffer output. The resulting output impedance

is typically 700Ω. Due to the limited drive capability, any additional

load must be carefully considered to avoid excessive start-up times

or absolute errors. In general, consider CMOChX buffering for the

following situations:

►

The VDD33 power rail of the AD4884 is frequently cycled.

►

Short start-up settling times are required.

►

If the external load on a CMOChX pin exceeds 30μA (RL < 45kΩ).

For the typical load regulation information, see Figure 30.

POWER SUPPLIES

The power requirements for the AD4884 are distributed across the

following supply domains:

►

AFE supply rails (±VS)

►

3.3V ADC analog circuit domain (VDD33)

►

1.1V ADC core supplies (VDD11ChA, VDD11ChB)

►

1.1V domain for the digital interfaces (IOVDDChA, IOVDDChB)

►

Optional internal voltage regulators input rail (VDDLDO)

The optional VDDLDO supply rail can be used to supply power

to the four integrated voltage regulators used to internally power

the 1.1V core (VDD11ChA, VDD11ChB) and interface (IOVDDChA,

IOVDDChB) rails. For all details and design considerations when

using the internal voltage regulators, see the Internally Regulated

Supply Configuration section. On the other hand, for more details

on applications that do not use internal regulators, see the External-

ly Generated Supply Configuration section.

Power for the VDD33 supply rail must be supplied from an external

source and must only be applied once power is supplied to the 1.1V

supply rails. For the full description of the activation order of the

voltage supplies, see the Power Supply Sequence section.

All supply domains are internally decoupled using multilayer, high

dielectric, ceramic capacitors (X6S), which eliminate the need of

external decoupling capacitors. However, care must be taken to

understand the bulk decoupling requirements for other components

in the design, which share the same supply. Integrated supply

decoupling capacitors in the AD4884 are listed in Table 6 and Table

Table 8. Supply Rails Integrated Decoupling Summary

Supply Pin

Nominal Capacitance

(μF)

Capacitance

Tolerance (%)

Return Path

+VS

0.44 (2× 0.22 )

±10

GND

−VS

0.44 (2× 0.22 )

±10

GND

VDD33

0.94 (2× 0.47)

±10

GND

VDDLDO

0.44 (2× 0.22 )

±10

GND

VDD11ChA

1.88 (4× 0.47)

±10

GND

VDD11ChB

1.88 (4× 0.47)

±10

GND

IOVDDChA

0.22

±10

IOGNDChA

IOVDDChB

0.22

±10

IOGNDChB

INTERNALLY REGULATED SUPPLY

CONFIGURATION

Each channel in AD4884 includes two internal LDO regulators, one

to generate the 1.1V VDD11ChX supply rail and another to internally

generate the 1.1V IOVDDChX supply rail. Upon power on or reset

of the AD4884 channel registers, both regulators automatically

power up when an external voltage source in the range of 1.4V to

2.7V is applied to the VDDLDO pins. Note that it is not allowed

to enable the internally regulated supply configuration for one

channel only. The regulators are designed to supply the internal

load requirement of the AD4884, therefore, no external loading is

permitted. Also, when using the internally regulated configuration,

the VDD11ChA, VDD11ChB, IOVDDChA, and IOVDDChB circuit nodes

must be kept separate (that is not shorted in any combination

among themselves). Note that, as described in the Power Saving

Operating Modes section, the IOVDDChX rails are disabled in both

power saving modes.

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