AD4884BBCZ datasheet(15/116 Pages) AD

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Data Sheet

AD4884

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. 0 | 15 of 116

Table 6. Pin Function Descriptions (Continued)

Pin Number

Mnemonic

Type1

Description

All pins specified as type DI, DO, or DI/O must use this ground reference.

IOVDDChB

Channel B ADC 1.1V Digital Interface Supply Rail. This supply is internally decoupled by a 220nF

capacitor to IOGND.

When power is supplied to VDDLDO (H6, H13), an internal LDO voltage regulator produces the 1.1V

required at this pin. The voltage regulator is automatically powered on when VDDLDO is driven with a

voltage between 1.4V and 2.7V.

If VDDLDO is left disconnected, the required 1.1V must be supplied to this pin from an external source

(typically the host controller interface supply).

K14

IOVDDChA

Channel A ADC 1.1V Digital Interface Supply Rail. This supply is internally decoupled by a 220nF

capacitor to IOGND.

When power is supplied to VDDLDO (H6, H13), an internal LDO voltage regulator produces the 1.1V

required at this pin. The voltage regulator is automatically powered on when VDDLDO is driven with a

voltage between 1.4V and 2.7V.

If VDDLDO is left disconnected, the required 1.1V must be supplied to this pin from an external source

(typically the host controller interface supply).

L2, L9, M2, M9

REFIN

3.0V Reference Voltage Input for ADCs. These pins must be shorted externally.

L6, L7

CNV+ChB, CNV−ChB

Channel B ADC Convert Start Inputs. This pin pair serves as the conversion control input, a conversion is

initiated on the rising edge of the convert signal.

These inputs are by default configured in complementary metal-oxide semiconductor (CMOS) mode, in

which CNV−ChB must be connected to IOGND and the convert signal is applied to CNV+ChB. In the LVDS

data interface mode, the convert start input can be optionally configured in LVDS mode, in which case, the

convert signal is applied differentially to CNV+ChB and CNV−ChB and an external 100Ω termination resistor

must be placed across these pins. For more details, see the ADC Conversion Control section.

L13, L14

CNV+ChA, CNV−ChA

Channel A ADC Convert Start Inputs. This pin pair serves as the conversion control input, a conversion is

initiated on the rising edge of the convert signal.

These inputs are by default configured in CMOS mode, in which CNV−ChA must be connected to IOGND

and the convert signal is applied to CNV+ChA. In the LVDS data interface mode, the convert start input

can be optionally configured in LVDS mode, in which case, the convert signal is applied differentially to

CNV+ChA and CNV−ChA and an external 100Ω termination resistor must be placed across these pins. For

more details, see the ADC Conversion Control section.

CLK+ChB/DCLKChB

Channel B ADC Data Interface Clock Multifunction Pin.

In LVDS data interface mode (default), this pin serves as half of the differential data clock input, and an

external 100Ω termination resistor must be present between it and the CLK−ChB pin.

In SPI data interface mode, the single-ended data clock signal must be applied to this pin.

CLK−ChB/DCSChB

Channel B ADC Data Interface Clock Input (CLK−ChB)/Data Interface Chip-Select (DCSChB) Multifunction

Pin.

In LVDS data interface mode (default), this pin serves as half of the differential data clock input, and an

external 100Ω termination resistor must be present between it and the CLK+ChB pin.

In SPI data interface mode, this pin functions as a chip-select input (data interface chip-select).

M13

CLK+ChA/DCLKChA

Channel A ADC Data Interface Clock Multifunction Pin.

In LVDS data interface mode (default), this pin serves as half of the differential data clock input, and an

external 100Ω termination resistor must be present between it and the CLK−ChA pin.

In SPI data interface mode, the single-ended data clock signal must be applied to this pin.

M14

CLK−ChA/DCSChA

Channel A ADC Data Interface Clock Input (CLK−ChA)/Data Interface Chip-Select (DCSChA) Multifunction

Pin.

In LVDS data interface mode (default), this pin serves as half of the differential data clock input, and an

external 100Ω termination resistor must be present between it and the CLK+ChA pin.

In SPI data interface mode, this pin functions as a chip-select input (data interface chip-select).

GPIO0ChB

DI/O

Channel B ADC General-Purpose Input and Output 0 Pin.

By default, this pin is enabled as an output and functioning as Channel B Configuration SPI SDO.

GPIO1ChB

DI/O

Channel B ADC General-Purpose Input and Output 1 Pin.

GPIO2ChB

DI/O

Channel B ADC General-Purpose Input and Output 2 Pin.

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