AD4884BBCZ datasheet(70/116 Pages) AD

70 / 116 page

Data Sheet

AD4884

DIGITAL INTERFACE

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Rev. 0 | 70 of 116

LVDS Output Differential Drive

The AD4884 LVDS interfaces support selection of the differential

output voltage from one of three predetermined differential ampli-

tudes of ±185mV p-p, ±240mV p-p, and ±325mV p-p, assuming

a termination resistance of 100Ω across the differential pair. The

output common-mode voltage of the LVDS driver is adjusted for

each selection automatically to ensure that the peak output voltage

remains within the IOVDDChX rail. The default setting is a differen-

tial amplitude of ±240mV p-p. The output differential voltage can

be independently configured for each channel by writing to the

LVDS_VOD bits of the corresponding ADC Data Interface Config-

uration C register (see the ADC Data Interface Configuration C

Data Interface Test Function

Regardless of the selected output configuration, the AD4884 is

equipped with an interface check function that is enabled by setting

the INTF_CHK_EN bit in the Data Interface Configuration A register

(see the ADC Data Interface Configuration A Register section,

Address 0x15).

The interface check function forces the data interface to output

a fixed, 16-bit pattern, which facilitates verification of the integrity

of the data interface physical layer, including device pads, PCB

interconnect, and the host interface connections. By enabling this

built-in test function, access to ADC conversion results is suspend-

ed, therefore, only use this function either at power-up or during

an idle period when conversion results are not required for normal

system function.

For more details, see the ADC Result Latency and LVDS Interface

Alignment section.

SPI DATA INTERFACE

SPI Data Interface Configuration

For applications that do not require the interface bandwidth of the

LVDS interface, such as when using asynchronous capture into the

result FIFO, the data interface of any channel can be reconfigured

into a single or quad lane, SPI data interface. In this configuration,

the channel outputs its data on either one or four CMOS data

lanes simultaneously at serial clock rates up to 50MHz. The result

data is shifted out serially on the falling edge of the interface clock

(DCLKChX). In SPI configuration, the channel results can be read

at an effective interface rate of up to 200MHz when using four SPI

lanes.

The SPI data interface for a channel is activated by setting the

DATA_INTF_MODE bit from its Data Interface Configuration A

section, Address 0x15). Once the data interface is configured

for SPI mode, the LVDS drivers are automatically disabled, includ-

ing the echo clock output (DCO+ChX and DCO−ChX), preventing

contention between LVDS and CMOS functions. As a result, the

LVDS_SELF_CLK_MODE and LVDS_VOD settings no longer effect

the operation of the data interface and can be left at their power-on

defaults or another convenient value. Because the driver is disa-

bled, the DCO+ChX and DCO−ChX output pins can, therefore, be left

disconnected in the hardware design as these pins are unused.

As detailed in Table 22, the following LVDS pins are reconfigured as

CMOS input or outputs to realize the SPI data interface.

Table 22. LVDS/SPI Data Interface Pins Crossreference

LVDS Pin

CMOS Pin

Function

CLK+ChX

DCLKChX

Data interface clock input

CLK−ChX

DCS ChX

Data interface chip select (active low) input

DA+ChX

SDOAChX

Serial Data Output A

DA−ChX

SDOBChX

Serial Data Output B

DB+ChX

SDOCChX

Serial Data Output C

DB−ChX

SDODChX

Serial Data Output D

As with LVDS configuration mode, SPI configuration selection al-

lows control of the number of active lanes. For SPI data interface

configuration, the user has the option to configure single lane SPI

or quad lane SPI.

SPI Active Data Lane Count

The SPI data interfaces can be configured to output the result

data on either one or four data lanes, which is controlled by the

SPI_LVDS_LANES bit in the ADC Interface Configuration A register

of each channel (see the ADC Data Interface Configuration A

lane active), and can be set to 1 to use four data lanes. Note that

this bit also sets the number of active data lanes for the LVDS

interface. The data order and pin assignment to the serial data

output (SDOxChX) pins is detailed in Table 23, and shown in Figure

124.

Table 23. SPI Data Lane(s) Data Order and Pin Assignment

Serial Data Output Pin

Output Data Order

One Active SPI Lane

(SPI_LVDS_LANES = 0)

Four Active SPI Lanes

(SPI_LVDS_LANES = 1)

SDOAChX

Not applicable

SDO 3

SDOBChX

SDO 0

SDO 2

SDOCChX

Not applicable

SDO 1

SDODChX

Not applicable

SDO 0

Data Interface CRC

To ensure the integrity of the result data, a CRC is appended

to the FIFO results. This CRC is always enabled and appended.

The computation of the result checksum is independent of that of

the configuration interface. The result is 24 bits in length and is

appended to each data result record acquired from the FIFO.

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