AD4884BBCZ datasheet(93/116 Pages) AD

93 / 116 page

Data Sheet

AD4884

CONFIGURATION REGISTERS

analog.com

Rev. 0 | 93 of 116

The features of the AD4884 family have been designed to simplify

the application of low latency data capture to a broad array of

measurement applications. This simplification is achieved through

customization of the data interface, data path, and data access

method for each channel, to satisfy both measurement and the host

processor interface requirements via the available configuration

registers.

Each channel has its own independent configuration memory,

accessible through its separate configuration SPI interface. The

by function to streamline device configuration as described in Table

30. As a result, the interface streaming functions (see Instruction

Mode Selection section) can be leveraged to simplify device con-

figuration to a single SPI frame consisting of an instruction word

and associated data. For most applications, modifications to the

are sufficient. Modification of content in the configuration interface

and product ID space (Address 0x00 to Address 0x11) is only

necessary to initiate a software reset or to change the configuration

access method. Note that changes to the configuration access

method are outside the scope of this document. For assistance with

these options, contact the local Analog Devices, Inc., sales office at

www.analog.com/sales, or submit a request for technical assistance

through the Precision ADCs page on the ADI Engineer Zone.

Table 30. Register Map Organization

Address Range

Function

0x00 to 0x11

Configuration interface and Product ID

0x14

Device status

0x15 to 0x17

Interface configuration

0x18 to 0x1B

Power and GPIO configuration

0x1C

General configuration

0x1C to 0x1E

FIFO configuration

0x1F to 0x24

Internal event detection

0x25 to 0x28

System error correction

0x29

Digital filter configuration

This section contains details about the functions of each of the bit fields. The access column in the register tables specifies whether the bit

fields are read-only (R), read/write (R/W), or write-1-to-clear (R/W1C) bits.

Table 31. Configuration Register Summary—Configuration Interface Functions (Address 0x00 to Address 0x11)

Addr Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset Access

0x00 INTERFACE_

CONFIG_A

[7:0]

SW_

RESET

RE-

SERVED

ADDR_

ASCENSION

SDO_

ENABLE

RESERVED

SW_

RESETX

0x10

R/W

0x01 INTERFACE_

CONFIG_B

[7:0]

SINGLE_

INST

RESERVED

SHORT_

INSTRUC-

TION

RESERVED

0x00

R/W

0x02 DEVICE_

CONFIG

[7:0]

RESERVED

OPERATING_MODES

0x00

R/W

0x03 CHIP_TYPE

[7:0]

RESERVED

CHIP_TYPE

0x07

0x04 PRODUCT_

ID_L

[7:0]

PRODUCT_ID[7:0]

0x5C

0x05 PRODUCT_

ID_H

[7:0]

PRODUCT_ID[15:8]

0x00

0x06 CHIP_GRADE [7:0]

GRADE

DEVICE_REVISION

0x02

0x0A SCRATCH_

PAD

[7:0]

SCRATCH_VALUE

0x00

R/W

0x0B SPI_

REVISION

[7:0]

SPI_TYPE

VERSION

0x83

0x0C VENDOR_L

[7:0]

VID[7:0]

0x56

0x0D VENDOR_H

[7:0]

VID[15:8]

0x04

0x0E STREAM_

MODE

[7:0]

LOOP_COUNT

0x00

R/W

0x0F TRANSFER_

CONFIG

[7:0]

RESERVED

KEEP_

STREAM_

RESERVED

0x00

R/W

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