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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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AD4884BBCZ bảng dữ liệu(PDF) 10 Page - Analog Devices |
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AD4884BBCZ bảng dữ liệu(HTML) 10 Page - Analog Devices |
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10 / 116 page  Data Sheet AD4884 SPECIFICATIONS analog.com Rev. 0 | 10 of 116 TIMING SPECIFICATIONS VDD33 = 3.3V ± 5%, VDDLDO = 1.5V to 2.7V, VDD11ChX = 1.1V ± 5%, IOVDDChX = 1.1V − 5% to 1.2V + 5%, VREFIN = 3.0V, fS = 20MHz, and TA = TMIN to TMAX, unless otherwise noted. Table 2. Timing Specifications Parameter Symbol Min Typ Max Unit Sampling Frequency fS 1.251 20 MHz Conversion Time tCONV 50 800 ns Acquisition Phase tACQ tCYC ns Conversion Cycle Period tCYC tCONV ns LVDS Data Interface Data Interface Clock Count N 8 Active Data Lane Count L 2 CNV±ChX High Time tCNVH tCLK 5 × tCLK tCYC − tCNVL ns CNV±ChX Low Time tCNVL tCLK 5 × tCLK tCYC − tCNVH ns CNV±ChX Edge to CLK± Rising Edge Alignment tCCA 535 ps CNV±ChX to Dx±ChX (MSB) Ready tMSB Gain Error Correction Enabled 20.5 22.4 ns Gain Error Correction Disabled 15.7 18 ns CLK±ChX Period tCLK 6.25 tCYC × L/N ns CLK±ChX Frequency fCLK 1/tCLK 160 MHz CLK±ChX to Dx±ChX Delay tCLKD 1 2.1 ns CLK±ChX to DCO±ChX Delay (Echo Clock Mode) tDCO 1 2 ns DCO±ChX to Dx±ChX Delay (Echo Clock Mode) tDCOD 0.02 1 ns SPI Data Interface Data Interface Clock Count, Single Conversion Result M 24 Active Data Lane Count C 1 4 Data Interface Chip-Select Falling Edge (DCSChX) to SDOBChX Data Valid tDEN 5 6 ns Data Interface Clock Period (DCLKChX) tDCK 20 ns Data Interface Clock Low-Pulse Width (DCLKChX) tDCKL tDCK × 0.45 ns Data Interface Clock High-Pulse Width (DCLKChX) tDCLKH tDCK × 0.45 ns Data Interface Clock Falling Edge to Data Remains Valid Delay tDHSDO 5 ns Data Interface Clock Falling Edge to Data Valid Delay tDDSDO 9.6 ns DCLKChX Rising to Data Interface Chip Select Falling tDCKEN 0 ns Data Interface Chip-Select High to DCLK Disabled tDCLKDIS 0 ns Data Interface Chip-Select High Between Frames tDCSMIN (tDCKEN + tDCLKDIS) + 0.5 × tDCLK ns Serial Configuration Interface SCLKChX Period tSCK 20 ns SCLKChX Low-Pulse Width tSCKL tSCK × 0.45 ns SCLKChX High-Pulse Width tSCKH tSCK × 0.45 ns SCLKChX Falling Edge to Data Remains Valid Delay tHSDO 0.7 ns SCLKChX Falling Edge to Data Valid Delay tDSDO 14.5 ns CSChX Falling Edge to SCLKChX tCSSCK 0 ns Last SCLK to CSChX Rising tSCKCS 0 ns SDIChX Valid Setup Time Before SCLKChX Rising Edge tSSDI 1 ns SDI Valid Hold Time After SCLK Rising Edge tHSDI 0 ns SCLK Rising to Data Interface Chip-Select Falling tSCKEN 0 ns |
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