công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

AD4884BBCZ bảng dữ liệu(PDF) 69 Page - Analog Devices

tên linh kiện AD4884BBCZ
Giải thích chi tiết về linh kiện  Dual-Channel 16-Bit, 20MSPS, SAR ADC with Analog Front End
PDF  116 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
Logo AD - Analog Devices

AD4884BBCZ bảng dữ liệu(HTML) 69 Page - Analog Devices

Back Button AD4884BBCZ Datasheet HTML 65Page - Analog Devices AD4884BBCZ Datasheet HTML 66Page - Analog Devices AD4884BBCZ Datasheet HTML 67Page - Analog Devices AD4884BBCZ Datasheet HTML 68Page - Analog Devices AD4884BBCZ Datasheet HTML 69Page - Analog Devices AD4884BBCZ Datasheet HTML 70Page - Analog Devices AD4884BBCZ Datasheet HTML 71Page - Analog Devices AD4884BBCZ Datasheet HTML 72Page - Analog Devices AD4884BBCZ Datasheet HTML 73Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 69 / 116 page
background image
Data Sheet
AD4884
DIGITAL INTERFACE
analog.com
Rev. 0 | 69 of 116
LVDS Data Transfer Latency
Where the user is concerned in knowing the overall latency from
when an individual ADC conversion is initiated to the time when
the LSB has reached the host controller, it is important to consider
the data transfer latency. The total latency observed is the sum of
the ADC latency and the data transfer latency, in this case, the
LVDS_CNV_CLK_CNT is set to achieve minimum ADC latency.
Additional clock cycles more than the minimum required incur
additional LVDS clock cycles of latency to the overall latency, as is
shown in Figure 117.
The data transfer latency on the LVDS interface depends on the
following parameters:
►
LVDS clock period, tCLK
►
Number of active LVDS lanes, NLANES
►
Number of bits to be read, NBITS
Calculate the latency as follows:
Data Transfer Latency =  NBITSNLANES×tCLK
For applications that require extremely low latencies, note that as
the data is transferred MSB to LSB in both single and dual lane
modes, and that there is no requirement to fully read a result from
the interface, the data transfer latency can be reduced for lower
resolution results (that is, NBITS can be chosen to be smaller than
the maximum bits available).
Figure 117. LVDS Data Transfer Latency



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com