AD4884BBCZ datasheet(80/116 Pages) AD

80 / 116 page

Data Sheet

AD4884

DIGITAL FEATURES

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Rev. 0 | 80 of 116

FIFO Timing Considerations

Immediate Trigger Mode

Figure 127 shows the timing relationship between the command

to arm the channel FIFO for data write access and the point at

which the FIFO is armed. Figure 127 shows an example of where

single lane SPI data access is configured and FIFO_FULL and

FIFO_READ_DONE are output to GPIO. Because a capture has

not yet been initiated, FIFO_FULL and FIFO_READ_DONE are

driven low. A free running CNV clock is shown in this example.

Upon receipt of the update to the general configuration register

(Address 0x1C), the FIFO controller advances to an idle state

on the next rising edge of CNV. The FIFO then advances to the

writing state after two further CNV clock edges and begins filling

the FIFO until WATERMARK results are loaded and FIFO_FULL is

generated.

Upon completion of reading the FIFO data, a rearming event for

immediate mode capture involves disabling the FIFO by writing 00

to FIFO_MODE then re-enabling by writing 01 to the FIFO mode

to arm the FIFO for a new capture. As is the case with the initial

arming, the FIFO advances to the idle state upon receipt of the first

rising edge of CNV after the configure instruction to arm the FIFO is

issued. The sequence and timing is the same as for the initial FIFO

arming. See Figure 127.

Figure 126. Immediate Trigger Mode Arming

Figure 127. Immediate Trigger Mode Rearming

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