AD4884BBCZ datasheet(53/116 Pages) AD

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Data Sheet

AD4884

DIGITAL INTERFACE

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Strict Access Selection and Multibyte

Registers

Several locations in the configuration memories of the AD4884

channels have been assigned as multibyte registers to support

the storage requirements. For example, the offset correct register

(see the Offset Correction Register section, Address 0x25) and

gain correction register (see the Gain Correction Register section,

Address 0x27) are multibyte registers because the resolution of

the correction coefficients they contain exceeds a single byte. For

a complete listing of multibyte registers, see the Configuration

Registers section. The length of each register, in bytes, is captured

in Table 31 in addition to other characteristic information.

The function of the STRICT_REGISTER_ACCESS bit is to indicate

to the interface controller that all bytes of a multibyte register must

be accessed in the current frame for valid communication to have

occurred. In the event a multibyte register is only partially accessed,

an interface fault is generated in the Interface Status A register

(see the Interface Status A Register section, Address 0x11), and

the partial content update is discarded. The intent of this restriction

is to ensure that corresponding configuration quantities are updated

in a manner that produces the desired device operation. The

access restriction function is enabled by default (STRICT_REGIS-

TER_ACCESS = 1) and can be disabled by clearing the access bit

(STRICT_REGISTER_ACCESS = 0) in the Interface Configuration

C register (see the Interface Configuration C Register section,

Address 0x10). With register access restriction disabled, each byte

of the configuration memory can be independently addressed, how-

ever, it is then incumbent on the software to correctly configure any

multibyte registers in the device memory to achieve the required

behavior.

The decision to enable or disable the register access restriction

has implications with regards to the correct construction of the

SPI frames containing one or more multibyte register accesses.

When STRICT_REGISTER_ACCESS is disabled, each byte of a

multibyte register is treated as a singular element. Furthermore,

the interface does not indicate a fault if all bytes of the register

are not programmed, or if the bytes are programmed in a random

order, and therefore, it is incumbent on the host to ensure that the

content of those registers are updated in a manner that produces

the required function in the device.

When STRICT_REGISTER_ACCESS is enabled, specific access

rules are enforced to ensure consistency between the data and the

expected behavior of the device. To understand how these rules

apply to multibyte registers in the configuration memory, it is impor-

tant to understand how the memory is organized. By convention,

multibyte registers are arranged in the configuration memory such

that the most significant byte of the register is stored in the most

significant address of the assigned register space, as shown in

Figure 93. As a result, the byte order of the register content trans-

mitted in the data phase is dependent on the ADDR_ASCENSION

selection.

Figure 93. Generic Byte Wide Memory, Multibyte Register Example

As shown in Figure 94, the address counter, by default, automat-

ically decrements (ADDR_ASCENSION = 0) such that the most

significant byte of the multibyte register is accessed first, followed

by the remaining byte(s) in that register in ascending order. Con-

versely, if ADDR_ASCENSION = 1, the least significant byte of the

multibyte register is accessed first followed by most significant byte.

As an extension of this concept, when STRICT_REGISTER_AC-

CESS = 1, any SPI frame that accesses a multibyte register as

the first entity in the data transfer must correctly set the starting

address in the instruction word to correspond to the ADDR_AS-

CENSION selection. In the case that the address counter automat-

ically decrements (ADDR_ASCENSION = 0), the starting address

is assigned to the register address for the most significant byte of

that multibyte register, and conversely, if configured to increment

automatically, the starting address must be set to the register

address for the least significant byte. As a result of the change

to ADDR_ASCENSION from automatic address decrement (0) to

automatic increment (1), Figure 91 and Figure 92 change as shown

in Figure 94 and Figure 95 to accommodate the changes in data

phase byte order and instruction phase multibyte register start

address.

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