AD4884BBCZ datasheet(71/116 Pages) AD

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Data Sheet

AD4884

DIGITAL INTERFACE

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Rev. 0 | 71 of 116

Sign Extension

When accessing FIFO data through a SPI data interface, the 16-bit

data length of AD4884 lends itself to easy data access and storage.

Hence, no sign extension is done, as opposed to 20-bit resolution

devices from the same family of products as AD4884, where sign

extension to 24-bits is performed.

GPIO PINS

The AD4884 GPIO pins are intended to simplify the development of

synchronous data acquisition applications by facilitating a simplified

state control interface between the host processor, the data con-

verter, and other related signal chain components. When configured

as an output, these GPIO pins can be assigned as an indicator of

device status, a digital control for a related signal chain component,

or a serial data lane for device configuration. In input mode, the

GPIO pins allow pin programming of converter features such as

digital filter synchronization (reset) and an external event trigger.

Each channel has its own set of GPIO pins that can be separately

configured.

The required function for each GPIO is defined by writing to the

GPIO Configuration A through GPIO Configuration C registers

(Address 0x19 through Address 0x1B), see the GPIO Configuration

A Register through the GPIO Configuration C Register sections.

The configuration for each GPIO includes an output enable bit,

an output data bit, and a function selection. The output data bit

determines the logical state of the output when the GPIO data

option is selected, otherwise, the output state is determined by

the selected function, assuming the output is enabled. By default,

GPIO0ChX is enabled as an output, and the configuration SPI SDO

function is selected. All other GPIO outputs are disabled.

Table 25 provides a brief description of the available AD4884 GPIO

functions. Each of the GPIO pins can be configured for any of the

following functions.

Table 24. GPIO Registers Overview

Bits

Contents

GPIO_CONFIG_A

GPIO_0_EN,

GPIO_1_EN,

GPIO_2_EN,

GPIO_3_EN

Enable bits for each GPIO.

0: Configures the GPIO as an input.

1: Configures the GPIO as an output.

GPIO_CONFIG_A

GPIO_0_DATA,

GPIO_1_DATA,

GPIO_2_DATA,

GPIO_3_DATA

The corresponding GPIO_x_SEL bit for each GPIO can be set to 0111b to read or write data to that GPIO.

In this mode, GPIO_x_EN selects whether each of these data bits is read only or write only, depending on whether the GPIO is

configured as an input or an output.

When configured as an output, these bits are write only, the user can set the bits to a logic level that they need to output on the

GPIO.

When configured as an input, these bits are read only, the user can read the bits to determine the logic level input to on the GPIO.

If the corresponding GPIO_x_SEL is not set to 0111b, the GPIO_x_DATA is not valid as the GPIO is overridden with the selected

GPIO function

GPIO_CONFIG_B

GPIO_0_SEL,

GPIO_1_SEL

Selection for the function mode of GPIO0 and GPIO1.

GPIO_CONFIG_C

GPIO_2_SEL,

GPIO_3_SEL

Selection for the function mode of GPIO2 and GPIO3.

Table 25. GPIO_x_SEL Function Descriptions

GPIO_x_SEL

Function

Description

0000b

Configuration SPI

SDO

Configuration Serial Data Output. This configures the selected GPIO to be the SDO for the configuration SPI.

0001b

FIFO full

FIFO Memory Full Indication Output. This configures the selected GPIO to function as an indicator that the channel FIFO is full. The

FIFO full indicator is set when the conversion result corresponding to the specified count in the FIFO watermark registers (see the

FIFO WATERMARK Register section, Address 0x1D and Address 0x1E) is loaded into the data FIFO. The FIFO full status bit is

cleared by reading data from the FIFO, and it is cleared when the first conversion result is moved from the FIFO to the data interface

output shift register.

0010b

FIFO read done

FIFO Memory Read Completed Output. This configures the selected GPIO to function as a FIFO read done indicator. The FIFO read

done indicator is cleared by default when the channel FIFO is first enabled, and each time the last conversion result is moved from the

FIFO into the data interface output shift register. The FIFO read done is cleared when the MSB of the last FIFO result is read on the

selected data interface.

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