AD4884BBCZ datasheet(51/116 Pages) AD

51 / 116 page

Data Sheet

AD4884

DIGITAL INTERFACE

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Rev. 0 | 51 of 116

Instruction Phase

An instruction phase immediately follows the assertion of the CSChX

pin (Logic 0) and is terminated by transmission of a complete

instruction packet or deassertion of CSChX. The instruction packet

starts with a single command bit indicating the operation type (Logic

1 for read and Logic 0 for write) that is then followed by the start

address for the operation. By default, the address is 15-bit long,

but the data interface has an optional short instruction mode in

which it is reduced to 7 bits. The short instruction mode is enabled

by setting the SHORT_INSTRUCTION bit = 1 in the Interface

Configuration B register (see the Interface Configuration B Register

section, Address 0x01).

Data Phase

Each instruction phase is immediately followed by an associated

data phase, during which data is either shifted out of the serial data

output (SDOChX) on the falling edge of SCLKChX (read access) or

is shifted into the device configuration memory through SDIChX on

the rising edge of SCLKChX (write access). The minimum size of the

data payload is defined as a single byte, however, it can include

multiple bytes depending on the depth of the register addressed

and the interface configuration settings for the SINGLE_INST and

STRICT_REGISTER_ACCESS bits (Register 0x01, Bit 7, and Reg-

ister 0x10, Bit 5, respectively).

Write Access

When CSChX is forced low, a new serial instruction phase begins.

The first bit sent in the instruction phase is the command bit, and

when it is forced low (Logic 0) this indicates a write operation. The

command bit is followed by an address that, for the write operation,

indicates where the information received in the subsequent data

phase is stored. As previously described in the Instruction Phase

section, the address has a default length of 15 bits, but the address

can be optionally shortened to 7 bits.

Following the instruction phase, an integer number of bytes con-

taining the data payload for one or more registers in the configu-

ration memory are transmitted to the AD4884 channel. The size

of the payload in this data phase is bounded by the selected SIN-

GLE_INST and STRICT_REGISTER_ACCESS interface options as

described in the Strict Access Selection and Multibyte Registers

section. Each data byte is loaded into the addressed register as

it is received, assuming the interface CRC is disabled. If the CRC

is enabled, however, the addressed data register is only loaded if

the internally computed checksum matches the CRC value received

from the host. In the event that the computed CRC and received

checksum from the host for a given entity are inconsistent, the

frame is treated as invalid as well. The checksum computation for

the interface CRC function is described in detail in the Configuration

Cyclical Redundancy Check (CRC) section.

Note that during the data phase of a write operation, the SDOChX

output is driven to Logic 0 when the product is not reporting the

latest CRC checksum to ensure a valid data state is presented to

the host controllers SDI pin.

Read Access

The SPI enables read access to the configuration registers to

validate previous configuration writes, read the device identification,

or verify the interface status.

When CSChX is forced low, a new serial instruction phase begins.

The first bit sent in the instruction phase is the command bit, and

when it is forced high (Logic 1) this indicates a read operation.

The command bit is followed by an address that, for the read

operation, indicates the start address for the register space to be

accessed. As previously described in the Instruction Phase section,

the address has a default length of 15 bits, but the address can be

optionally shortened to 7 bits.

During the subsequent data phase, content from the addressed

the falling edge of SCLKChX. The number of bytes transmitted in

any one data frame is determined by the interface configuration set-

ting selections for the SHORT_INSTRUCTION and STRICT_REG-

ISTER_ACCESS options as demonstrated in the examples shown

in the Instruction Mode Selection and the Strict Access Selection

and Multibyte Registers sections.

Instruction Mode Selection

The configuration interface memory controller defaults to streaming

mode upon power up (SINGLE_INST = 0). In streaming mode, mul-

tiple, contiguous registers are accessed in a single SPI frame, start-

ing at the address specified in the instruction phase. In streaming

mode, only one instruction phase is permitted per SPI frame, requir-

ing a new SPI frame be initiated for changing access commands

or otherwise access a noncontiguous address in the register space.

For each byte transferred during the subsequent data phase, the

internal address counter is automatically updated according to the

setting of the ADDR_ASCENSION bit in the Interface Configuration

A register (see the Interface Configuration A Register section), in

the way specified by Table 15.

Table 15. Address Ascension Selection

ADDR_ASCENSION Bit

Value

Address Controller Behavior

(STRICT_REGISTER_ACCESS = 1)

0 (Default)

Decrement Address. Multibyte registers are accessed

by addressing the most significant byte address.

Increment Address. Multibyte registers are accessed

by addressing the least significant byte address.

Figure 91 shows the generic SPI frame formatting for a serial trans-

action using the default interface configuration. In this example,

a portion of the configuration register space consisting of a byte-

wide register and a multibyte register is accessed. The address

for the byte-wide register resides in the most significant address

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