AD4884BBCZ datasheet(63/116 Pages) AD

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Data Sheet

AD4884

DIGITAL INTERFACE

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Rev. 0 | 63 of 116

LVDS DATA INTERFACE

LVDS Data Interface Configuration

The LVDS interface of each channel consists of up to five pairs

of differential signals. The data clock input pair (CLK+ChX and

CLK−ChX), echoed data clock output pair (DCO+ChX and DCO−ChX),

two data output lanes (DA+ChX and DA−ChX , DB+ChX and DB−ChX ),

and optionally, the conversion clock can be configured as either an

LVDS pair (CNV+ChX and CNV−ChX) or as a CMOS using CNV+ChX,

where for this case, CNV−ChX is connected to GND. This user

selection is configured using the LVDS_CNV_EN bit in the ADC

Data Interface Configuration B register (see the ADC Data Interface

Configuration B Register section, Address 0x16). The data lanes

use a DDR scheme, which allows a single lane at the maximum

interface clock speed of 160MHz to transfer the full maximum

throughput of 320Mbps of the channel. Dual lane can be enabled

to reduce interface clock speed and ease synchronization (see

the ADC Data Interface Configuration A Register section, Address

0x15). By default, LVDS with one active lane is selected as the

primary data interface for accessing conversion results.

To achieve maximum channel throughput, it is necessary that while

a conversion is performed the result of the previous conversion

is read. For this reason, it is critical that both the rising and

falling edges of CNV+ChX and CNV−ChX are closely time aligned

to the rising edge of CLK+ChX and CLK−ChX. To avoid introducing

noise into the conversion result, the CLK+ChX and CLK−ChX edge

placement must be aligned to within ±535 ps (tCCA) of the interface

clock (CLK±ChX), as specified in Table 2.

The data interface is highly configurable allowing the customization

of the output stream to meet a wide range of applications. Configu-

ration options include the number of active lanes (1, 2), self clocked

and echo clock modes, interface test functions, and data encoding.

LVDS interface mode is used in applications where continuous

conversion at channel sampling rates exceeding 1MHz is required.

Transmission of the result data occurs MSB first and is output after

the amount of time specified in detail in the ADC Result Latency

and LVDS Interface Alignment section.

LVDS Active Data Lane Count

The LVDS interface can be configured to output the result data on

either one or two data lanes, which is controlled for each channel

by the SPI_LVDS_LANES bit in their respective ADC Data Interface

Configuration A register (see the ADC Data Interface Configuration

A Register section, Address 0x15). By default, this bit is set to 0

(one lane active), and setting SPI_LVDS_LANES = 1 uses two data

lanes. Note that this bit is also used to configure the number of

active data lanes for the SPI.

In single lane operation, Data Lane A (DA+ChX and DA−ChX signal

pair) is enabled as the primary data output, and the conversion

result is shifted out serially, MSB first, using 8 interface clocks

applied to CLK+ChX and CLK−ChX inputs per conversion. The result

data is shifted out of the device on each edge of the echo clock

outputs, DCO+ChX and DCO−ChX. The result MSB (D15) and all odd

numbered data bits are output on the falling edge of the interface

clock. Conversely, the even numbered data bits are output on the

rising edge of the interface clock.

In dual lane configuration, the result data is shifted out in parallel,

2 bits per clock edge, MSBs first. As a result, only four interface

clock cycles are required per conversion. As the data access period

is equivalent to the conversion period, the interface clock frequency

is reduced by a factor of two relative to the single lane case. For

the timing and latency implications of having different clock periods

in the single lane and dual lane configurations, see the ADC Result

Latency and LVDS Interface Alignment section.

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