AD4884BBCZ datasheet(66/116 Pages) AD

66 / 116 page

Data Sheet

AD4884

DIGITAL INTERFACE

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Rev. 0 | 66 of 116

LVDS Manchester Encoding Mode

This mode is accessed via the ADC_DATA_INTF_CONFIG_B reg-

ister (see the ADC Data Interface Configuration B Register section,

Address 0x16), which produces Manchester encoding of the result

data in compliance with IEEE 802.3. This mode can be used in iso-

lated data applications where the converter supplies can be floated

and the data outputs capacitively coupled to the host controller. By

ensuring that the mean output of each data lane is 0, the receiver

side common-mode voltage is not disturbed by the result pattern.

Manchester encoding is available in dual lane LVDS mode only so

that the maximum data throughput is achievable with the maximum

160MHz LVDS clock rate.

Figure 114 shows an example how this isolation can be implement-

ed. Note that the LVDS 100Ω termination resistor prior to the

isolation capacitors is required.

Figure 114. Isolated LVDS

ADC Result Latency and LVDS Interface

Alignment

When an AD4884 channel is configured for LVDS interface mode,

each conversion result is placed into its LVDS interface output

shift register(s). The LVDS_CNV_CLK_CNT bits in the ADC Data

Interface Configuration B register (see the ADC Data Interface Con-

figuration B Register section, Address 0x16) are used to configure

the point in time when the conversion result data is loaded into the

LVDS interface output shift register(s), but note that the number of

clock counts is not encoded in straight binary, see Table 20. The

total time from the rising edge of a convert pulse to when the MSB

of that conversion request is internally available to transfer to the

output register is defined as (tCYC + tMSB), both specified in Table 2.

Because the transfer of this result data is under the control of the

LVDS of CLK+ and CLK−, there is an additional (1.5 × tCLK) that

must be allowed to guarantee a fully completed result is transferred

to the interface for read back. The user must calculate the correct

required LVDS_CNV_CLK_CNT value and configure the ADC Data

Interface Configuration B register (see the ADC Data Interface

Configuration B Register section) according to the conversion rate

and tCLK used.

For minimum latency, the correct LVDS_CNV_CLK_CNT value to

use for a particular conversion rate is calculated as (tMSB/tCLK +

1.5). This number is rounded down to the nearest integer value.

If gain error correction is enabled (see the Gain Error Correction

section), the maximum tMSB time is specified as 22.4ns. For a

20MSPS conversion rate in single lane LVDS with a 160MHz LVDS

clock, the minimum LVDS_CNV_CLK_CNT is calculated as 22.4ns/

6.25ns + 1.5, yielding a rounded down value of 5. Conversion

latency is then determined as time, aligned to the falling edge of

the CLK signal, described as tMSB_READ or latency in the timing

diagram, which can be calculated as (LVDS_CNV_CLK_CNT + 0.5)

× tCLK. For the given example, the resulting single lane latency is

then (5 + 0.5) × 6.25ns + tCYC = 84.38ns.

Taking a dual lane example with the LVDS clock running at half the

speed (80MHz), again having 20MSPS and gain error correction

enabled, the same formula is used and yields (22.4ns/12.5ns) +

1.5, resulting in an LVDS_CNV_CLK_CNT of 3, and a result for

latency of (3 + 0.5) × 12.5ns + tCYC = 93.75ns.

With gain error correction disabled (see the Gain Error Correction

section), the maximum tMSB time is specified as 18ns. For a

20MSPS conversion rate in single lane LVDS with a 160MHz

LVDS clock, the calculation becomes (18ns/6.25ns) + 1.5, yielding

a setting of 4 for the LVDS_CNV_CLK_CNT. Conversion latency

is then determined as time, aligned to the falling edge of the CLK

signal, described as tMSB_READ or latency in the timing diagram,

which can be calculated as (LVDS_CNV_CLK_CNT + 0.5) × tCLK.

Then in this case, the single lane latency is calculated as (4 + 0.5) ×

12.5 + tCYC = 78.13ns latency.

Once again, taking the previous example to a dual lane case with

the LVDS clock running at half the speed (80MHz), again having

20MSPS and gain error correction disabled, the formula then be-

comes (18ns/12.5ns) + 1.5, resulting in an LVDS_CNV_CLK_CNT

of 2, and a result for latency of (2 + 0.5) × 12.5ns + tCYC = 93.75ns.

The four examples above are calculated to achieve minimum laten-

cy, but it is possible to use a higher LVDS_CNV_CLK_CNT value,

whereby latency is increased by tCLK for each +1 unit increase in

the LVDS_CNV_CLK_CNT value.

Figure 115 and Figure 116 serve as aids to describe the placement

of the ADC result data onto the LVDS interface controlled by

the LVDS_CNV_CLK_CNT, showing that a new result is internally

completed after tCYC + tMSB, signified here also by a notional

tMSB_AVAILABLE (introduced only for the purposes of the explanation

in Figure 115 and Figure 116). Figure 115 shows an example

at 20MSPS conversion rate, with gain error correction, 160MHz

LVDS clock, single lane, and shows that the LVDS_CNV_CLK_CNT

setting of 5 is the earliest the conversion result can be loaded to

the LVDS interface under these conditions. One additional full tCLK

cycle is required (a complete cycle being CLK+ChX falling edge

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