AD4884BBCZ datasheet(32/116 Pages) AD

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Data Sheet

AD4884

THEORY OF OPERATION

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Rev. 0 | 32 of 116

POWER SAVING OPERATING MODES

The operating mode of each AD4884 channel is controlled by the

OPERATING_MODES bits in its corresponding Device Configura-

tion Register (Address 0x02). On power up and after reset, the de-

fault is normal mode (OPERATING_MODES = 00). Table 10 shows

all operating modes, and Figure 57 shows the allowed transitions

between these modes. Note that direct transitions between the two

power saving modes (standby and sleep mode) are not permitted.

It is important to stop all conversion and data interface clocking to a

channel before configuring its power mode.

When both ADC channels have been put in either standby mode or

sleep mode, the VDD33 supply can be removed to reduce power

consumption. This supply must be reestablished prior to issuing the

SPI configuration interface commands to exit either power saving

mode.

Figure 57. Operating Mode Transitions

Transitioning from normal mode to either of the two power saving

modes is achieved by writing the required value to the OPERAT-

ING_MODES bits in the Device Configuration Register. Waking

up (that is, transitioning back to normal mode) is achieved in a

similar way because the SPI configuration interface operation is

not affected by any of the power saving modes (see the SPI Config-

uration Interface section). Standby mode can be selected to save

power, in the case where the user wants to quickly return to normal

conversions. Sleep mode is a lower power state where returning to

normal mode takes longer. Both standby and sleep mode can be

particularly useful when used with the result FIFO (see the Result

FIFO section), whereby previously stored conversion data can be

accessed from the FIFO while it is still in the selected power saving

mode.

When using the internally regulated supply configuration, putting

a channel into standby or sleep mode powers down the LDO

regulator generating its corresponding IOVDDChX rail. This disables

all inputs and outputs under the now unpowered IOVDDChX domain

(all corresponding GPIOxChX, LVDS data interface (see the LVDS

Data Interface section) and SPI data interface (see the SPI Data

Interface section) signals are disabled). Note that in this condition,

it is still possible to write to the AD4884 SPI configuration to

issue a command to return to normal mode by writing to the

OPERATING_MODES bits in the device configuration register (see

the Device Configuration Register section) or to issue a software

reset (see the Software Reset section), because CS ChX, SCLKChX,

and SDIChX are under the VDD11ChX supply domain. As GPIOxChX

is disabled, it is not possible to perform any read activity on the SPI

configuration interface bus.

When IOVDDChX is externally supplied, and the channel is put

into standby or sleep mode, its LVDS data interface is disabled,

however, all its GPIOxChX, SPI data interface, and SPI configuration

interface pins remain enabled and unaffected. While power is sup-

plied externally to IOVDDChX within its specified range, previously

acquired data stored in the channel result FIFO can be access in

either standby or sleep mode.

Table 10 also indicates the wake-up times associated with each of

the modes. Wake-up time from sleep mode is significantly higher

than that of standby mode because time must be allowed for

the internal reference and common-mode buffers to reenable and

to replenish charge to the internal capacitors. Wake-up time is

defined as the interval between writing the SPI command that

exits the selected power-saving mode to the device configuration

pulse can be applied. Applying conversion start pulses before the

specified wake-up time has elapsed can lead to improper operation

or permanent device damage.

For the lowest power consumption of a channel in any of the power

saving operating modes, the LVDS_SELF_CLK_MODE must be

enabled in its ADC Data Interface Configuration B register (see

the ADC Data Interface Configuration B Register section) to power

down the LVDS DCO transmitter.

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